Case study of PID control in an FPGA

Paul Schad and David Carney, Plexus

January 17, 2011

Paul Schad and David Carney, PlexusJanuary 17, 2011

This paper provides an account of how to design and verify an FPGA PID controller. The presented design uses PID to control a constant power pulse. The FPGA measures voltage and current and controls those measurements to a power setpoint.

This article is from a class at DesignCon 2011. Click here for more information about the conference.

Its output is a DAC value that controls an electronic load connected to the source. A previous generation product used a single board computer for PID control, but the loop sample rate was not fast enough for the nextgen product.

A DSP was considered, but there was already an FPGA present in the previous generation so we investigated how to take advantage of it to solve this design problem. Most FPGAs have embedded multipliers to allow easy implementation of DSP operations, and they are potentially faster than a DSP because they can parallelize tasks including the calculations, external communications, and multiple control loops if applicable.  We will also provide detail on the design problems inherent in doing PID control in an FPGA.

We will also cover how we selected a PID equation, the architecture of the FPGA, and the system level timing analysis. Addressed are some of the implementation details including how to implement the multipliers, considerations with fixed-point math, resource usage, and tuning methods. Finally, the paper will cover how the design was verified with a test bench.

How to select a PID equation
The traditional analog PID equation is given as follows [1].

The adjustable PID parameters are K, TI and TD, while u(t) is the control output, and e(t) is the error signal (setpoint response level – measured response). The pulse transfer function of the digital PID controller is given as follows [1].

For the purposes of digital implementation, it is convenient to express this equation in incremental discrete sampled form using backward differences as follows [2].

The terms of this equation are defined as follows:

k = sample number

Ts = sample period

e(k) = error term = SP(k) – y(k)

SP(k) = setpoint value to control measured input to

y(k) = input value being controlled

u(k) = controller output value

KP = the gain of the proportional control

KI = the gain of the integral control

KD = the gain of the derivative control

This form of digital PID control is often referred to as Type A [3]. Two additional forms of the equation have been used by engineers to improve the response in real world systems. Type B is created by removing the setpoint from the calculation of the KD term and is shown as follows [3].

Type C is created by further removing the setpoint from the calculation of the Kp term and is shown as follows [3].

These so called Type B and Type C equations are a special case of setpoint weighting in which the setpoint weighting factors for both proportional and derivative control are set to 0. Eliminating the setpoint from the proportional control gives a smoother response with less overshoot when large changes in the setpoint occur.

Eliminating the setpoint from the derivative control limits the transients that occur in the output response due to large changes in the setpoint. Reducing the derivative response also improves the control loop behavior in the presence of high frequency noise disturbances [2].

In general, it is easier to achieve a stable desired response with the setpoint value removed from the proportional and derivative terms of the PID controller. The Type C equation was chosen for this application for these reasons.

System-level simulation
Matlab Simulink was used to simulate the behavior of the entire control loop system with a Type C digital controller equation. Two aspects of the FPGA architecture were studied in this simulation. The first was the Type C equation, and the second was the effect of a 5.877 µs delay between taking a current and voltage sample and updating the DAC output (see System Timing Analysis section for details on this delay). Below in Figure 1 below is the top-level diagram of the Simulink simulation.


Figure 1: Simulink Model (To view larger image click here)

This simulation takes into account an inner and an outer control loop. The inner loop consists of the analog hardware (current sensor, electronic load MOSFET, error amplifier, and compensator), and is everything to the right of the DAC and ADCs in the figure. Everything to the left is part of the outer control loop implemented in the FPGA.

In addition to this simulation, the inner loop was tested using an arbitrary waveform generator in the lab, meant to simulate the changing output of the DAC, and monitored with an oscilloscope on the load. The results from the testing and simulation showed that the Type C equation was acceptable so we did not implement and test any of the other equations.

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