Debugging FPGA-based video systems: Part 1
Editor’s Note: In this two part series from Digital Video Processing For Engineers, Andrew Draper describes some of the strategies for debugging an FPGA-based video system to be sure it reliably delivers video streams in real time. Part 1: Timing analysis and debugging.
In this series of articles we will discuss some strategies for debugging a video system built in an FPGA. The examples use Altera’s video debugging tools and methodology, although the concepts can be applied generally.
Before moving on to the video-specific parts of debugging it is worth checking that the design has synthesized correctly and has passed a number of basic sanity checks.
Hardware designs that run from a clock need to meet a number of timing constraints. The two most basic of these exist to prevent errors if a signal changes while it is being sampled by a register: The input to a register must be stable for a time before the clock edge on which it is sampled e referred to as the setup time (Figure 21.1).
Figure 21.1. Setup and hold times
Most signals originate from registers in the same clock domain, the outputs of which change just after the clock edge (i.e. there is a delay going through the register). There are also delays while the signals pass through combinational logic, and further delays if the signals need to be routed across the chip to their destination. The sum of these delays is known as the propagation delay. The mathematical relationship between the delays is expressed by the following two equations which must be satisfied for all paths within the chip:
propagation delay þ setup time < ¼ clock period
propagation delay > ¼ hold time
Where < ¼ is the mathematical less than or equal symbol, and > ¼ is greater than or equal There are more complex timing issues when signals cross from one clock domain to another but these are usually handled by specially designed library components.
A hardware design where these equations are satisfied for all signals on the chip is said to meet timing. A design which does not meet timing will usually fail in subtle and unexpected ways so further debugging is not usually productive.
Check that the Design Meets Timing
During synthesis the layout tool will place the logic within the chip and then run a timing analysis to check that the design meets the setup and hold requirements of the chip that will implement it. If these requirements are not met, the tool will adjust the layout and run the timing analysis again, continuing until timing analysis passes.
For the timing analysis stage the designer must provide scripts to tell the tool what timing behavior is required. These scripts are written by the hardware designer and shipped with the library component (if you write your own hardware with multiple clock domains then you will need to provide these scripts). If these scripts are incorrect, or if the clock speeds set in the scripts are lower than the actual speed of the clock, then the design can fail even if it meets timing.
A timing failure in one part of the circuit can cause problems elsewhere in the design, because if one part of the design fails to meet timing then the tool will stop rearranging the design throughout the chip. It will report the errors that have caused it to stop processing, but may suppress errors for other areas of the design which have not been completely processed. Thus a timing failure in one part of the chip is said to hide failures elsewhere in the design.
The propagation delay varies with several factors: The temperature of the silicon within the chip: recent chips run fastest at room temperature and slowest at the top and bottom ends of their temperature range. Manufacturing variations can change the propagation delay between one batch of chips and the next.
Manufacturers partly deal with this by measuring the speed of chips after production and assigning a higher speed grade (and price) to those with lower propagation delays but there is still a small variation within each speed grade.
Small changes in the supply voltage: tolerances within the power supply components allow for difference between the supply voltages from one board to another. The timing analysis tool will usually check the timing multiple times with different timing modes e for example it will check both the maximum and minimum propagation delays for the temperature and manufacturing variation.
All timing models for a design must pass before it can be used in a production system is used when timing passes only at lower temperatures: a liberal application of freezer spray to the chip can make a design work for a minute or two e often long enough to indicate that timing is the cause of failures.