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# The basics of sigma delta analog-to-digital converters

February 12, 2013

For the benefit of software and hardware developers whose experience has been mainly in the digital domain, we provide a review of the basics of sigma delta (SD) analog to digital converters (ADCs). It will be useful to a designer as a review, whether implementing an ADC on a board to work with associated digital components, or in a more complex SoC environment. We explain the functioning of all components by using an analog input example. Many different parameters used with respect to sigma delta ADCs are also explained. (This article is meant to be read as a companion to Mixed Signal Verification of Sigma Delta ADCs in an SoC environment.

An SD-ADC has a modulator and a digital filter (also known as decimation filter) as shown in Figure 1. A modulator converts the input analog signal into digital bit streams (1s and 0s). One can observe a bit, either 1’b1 or 1’b0 coming at every clock edge of the modulator.

The decimation filter receives the input bit streams and, depending on the over sampling ratio (OSR) value, it gives one N-bit digital output per OSR clock edge. For example, if we consider OSR to be 64, then the Filter gives one N-bit output for every 64 clock edges (64 data outputs of the modulator). Here N is the resolution of the SD ADC. Click on image to enlarge.

Figure 1: Signal flow diagram in a first order Sigma Delta ADC

How a modulator works

The working of a modulator can be explained using a conversion example. In Table 1 the headings X, B, C, D, and W correspond to points in the signal path of the block diagram in Figure 2. For this example, the input X is a DC input of 3/8. The resultant signal at each point in the signal path for each signal sample is shown in Table 1.

Note that a repetitive pattern develops every sixteen samples, and that the average of the signal W over samples 1 to 16 is 3/8, thus showing that the feedback loop forces the average of the feedback signal W to be equals to the input X. Figure 2: First order sigma delta block diagram Table 1

The data D is received by the decimation filter, which generates an N Bit output. In the above example, if the averaging (or OSR) is less than 16, then there will be a quantization error. This is because the feedback loop has not been giving sufficient time for the output to reach the value of the input. Hence, a sigma delta ADC’s accuracy/SNR improves with increasing OSR value, provided the input frequency is very slow. Also, even if the OSR is greater than 16, if resolution of the SDADC (the value N) is less than 8, then there will be a finite quantization noise, the reason being the resolution of the ADC is less than the granularity of the Signal.
From a frequency domain perspective, when the input signal passes through the modulator, the white noise shifts to a high frequency noise in the frequency domain, as shown in Figure 3, but the signal frequency does not shift. The decimation filter, being a low pass filter, then cuts off the high frequency components.   Figure 3: Showing how the quantization noise transforms into a high pass shape

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