Saving your embedded printed circuit board design with forensic technology

Zulki Khan, NexLogic Technologies

May 29, 2013

Zulki Khan, NexLogic TechnologiesMay 29, 2013

Continually shrinking printed circuit boards (PCBs) populated with greater numbers of package-on-package (PoP) devices have made it tougher for design engineers to locate causes of system failures. After spending many hours or days trying to uncover design defects and flaws using traditional methods such as automated optical inspection (AOI) or x-ray, design engineers may simply give up and discard their designs, losing the time and considerable money they’ve invested in them, simply because they cannot locate the culprit making their designs inoperable.

(AOI) or x-ray are highly reliable tools for conventional inspection but they aren’t always able to detect elusive defects such as a micro hairline fracture within a solder joint, as shown in Figure 1, or black pad or minute solder pin holes not seen at the 300 or 400 magnification level.

Figure 1: Micro hairline fracture within a solder joint

Forensics to the rescue
Forensic technology may succeed where conventional inspection fails, in particular with advanced technologies like PoP. Board forensics using inspection kits consisting of scanning electron microscopes (SEM) and time domain reflectometry (TDR) are key sleuthing tools.

Figure 2 shows an impedance control chart with 90 ohms impedance shown on a TDR report with a 5 percent tolerance.

Figure 2: 90 ohms impedance shown on a TDR report with 5% tolerance

Forensic tools and techniques provide the microscopic detective work and uncover a variety of tiny design or manufacturing problems that automated optical inspection (AOI) or x-ray may miss.

Designing to avoid use of forensics
Embedded systems designers are faced with a myriad of new challenges posed by continually shrinking boards and advanced component packaging, like PoP.

One such area is 0.3 mm ultra-fine ball grid array (BGA) pitch design. In this case, as of this writing, there are no Association Connecting Electronics Industries IPC standards or guidelines for ultra-fine BGA pitch levels below 0.5 mm pitch. So, the savvy PCB designer pulls from his or her bag of tricks to perform the most efficient design possible.

Part of that is keeping in mind that land patterns are especially tight. The PCB designer knows that only one set of traces can go between the pads of these ultra-fine pitch BGA devices. But if two are used, manufacturing issues arise. Moreover, it’s critical for the PCB designer to assure the fabrication house has the necessary leading-edge technology to deal with a high-caliber board that supports ultra-fine BGA pitch below 0.5 mm.

Stringent control of a design’s transmit and return path is another key consideration. It should be as short as possible. The last thing the PCB designer wants is to create ripples in transmission and reception. Therefore, the tolerances of those impedance control traces should be extremely tightly matched. Tolerance should be within one to two percent with a five percent maximum. This creates a very clean eye diagram and keeps signal to noise ratios (SNRs) under control once the design is completed and undergoes simulation.

The PCB designer also has to take into account the fact that boards are not only getting smaller, but thinner. Earlier, the industry dealt with 62 mil thickness boards; now, providers are working with 47 and 31 mil and even thinner boards. The role the PCB designer plays in this case is to accurately define a panel size for small boards to assure optimal printing and placement.

Testing also becomes more challenging with these designs. For one, test pad points are shrinking. Therefore, finer test points must be defined to assure they are proper for flying probe or in-circuit test (ICT). These test points should be big enough to accommodate the probing of flying probe test, yet small enough relative to the size of an ever-shrinking board. The question for the PCB designer is where to place test points. Should they go on the component side where all the decoupling capacitors are connected or on the bottom side of the BGA?  Considering that everything is shrinking – the board and packaging – test points are placed on the bottom side of the BGA most of the time since there’s little real estate left.

This also means creativity plays a major role in these designs. Instead of testing individual components at one time, like before, the PCB designer now has to design in a method whereby a module of the circuit can be tested from few test point locations; thereby the need of a vast number of test points is greatly reduced.

A further challenge is that passives continue to become dramatically smaller. For example, the newest 01005 package is half the size of the 2001, which is about the size of a grain of salt. The 01005 has to be machine placed; otherwise, there’s no other way for it to be placed on a board or to be reworked at a later stage.

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