Asynchronous reset synchronization and distribution – challenges and solutions

July 28, 2017

dobkin-July 28, 2017

In addition, for large designs, the skew inside the reset and clock distribution networks can be significant due to design (unequal wire length, unequal load, IR drop) and process (buffer and wire) variations. The relationship between reset and clock signal arrivals may vary for different flip-flops ‎[2]. In that case, different parts of the design may leave reset state on different clock cycles, violating the required functionality. An example is shown in Figure 2, where the release edge of RESET arrives at flip-flops Q0 and Q1 on different clock cycles, leading to a non-current release of the flip-flops from their reset states.

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Figure 2: Reset and Clock skew in large designs (Source: vSync Circuits)

To avoid the aforementioned problems, an asynchronous reset release must be synchronized to a targeted clock. A classic reset synchronization is performed by means of special reset synchronizers that are employed at the root of the reset distribution network. A number of such synchronizers are shown in Figure 3.

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Figure 3: Asynchronous reset synchronizers: (a), (b) "trailing-edge" synchronizer; (c), (d) "vdd-based" synchronizer; (e) reset synchronizer operation; (f) reset release timing path (Source: vSync Circuits)

In "trailing-edge" synchronizers, shown in Figure 3a and Figure 3b, the incoming asynchronous reset RSTI signal is connected to the synchronizer output RSTO through a combinational logic (OR and NAND gate examples are shown), allowing an asynchronous RSTO assertion following a RSTI assertion. Thus, the RSTO assertion does not depend on the clock. Note that in synchronizer of Figure 3a both RSTI and RSTO are active high signals, while in synchronizer of Figure 3b the input RSTI_N is active low, while RSTO is active high. On the asynchronous release of RSTI, the output RSTO is kept asserted until the RSTI release is synchronized by means of the two-flop synchronizer (F0, F1). Then, RSTO is released synchronously, satisfying setup and hold conditions towards the flip-flops connected down the reset distribution network.

The operation of the reset synchronizer is shown in wave diagram of Figure 3e. While being synchronous, the latency of the reset release can vary by one clock cycle due to a possible metastability of the F0 flip-flop. It should be also noted that the number of flip-flops employed in a synchronizer shall be set according to MTBF ‎[4] computation, however, thanks to a very low rate of RSTI, in most of the cases, two flip-flops provide a satisfactory MTBF.

Figure 3c and Figure 3d show another common flavor of asynchronous reset synchronizer. In this "vdd-based" synchronizer, flip-flops with asynchronous reset/set port are employed (note that the trailing-edge synchronizer employed simple D-flip-flops without RST/SET ports). At RSTI assertion (Figure 3c), the output of the synchronizer RSTO_N (active low) asynchronously becomes asserted regardless of the clock activity. On the RSTI release, the VDD signal ("1") connected to the D port of flip-flop F0 is synchronized. F0 may become metastable, however, since the input of F1 does not change on the first clock edge, F1 is not subject for a metastability. Thus, the constant "1" input is synchronized using a two-flip-flop synchronizer, leading to an asynchronous release of RSTO_N.

The vdd-based synchronizer has an advantage over trailing edge one since it can work without a clock at all, namely the clock may appear after the RSTI release. The trailing edge synchronizer requires a stable clock (at least for a few cycles) before the RSTI release, otherwise its internal flip-flops are not initialized.

Figure 3f shows the timing path related to reset release between the synchronizer flip-flop F1 and a targeted application flip-flop F2. As can be observed, since both flip-flops F1 F2 reside in the same clock domain, the path TR shall be optimized according to standard STA rules, namely, should be shorter than the clock cycle and should satisfy setup and hold conditions towards all destination flip-flops, e.g. F2.

Denoting the reset distribution network latency as TR, and a clock cycle as TCLK, the design should satisfy the following expression (for simplification, FF1 propagation delay is assumed to be included in TR and the clock skew is neglected):

TCLK >= TR+ TSU       … (1)

Evidently, the timing conversion for reset distribution networks is challenging in the following cases:

  1. Large reset distribution network. When the number of flip-flops inside a clock domain is large, the reset distribution network latency TR becomes high, possibly larger than a single clock cycle, thus violating the timing constraint (1).

  2. Fast clock rate. When a fast clock is employed, the clock cycle TCLK becomes short, challenging constraint (1).

Modern high performance designs, having a large number of flip-flops and operating at high frequencies, require special solutions for handling the reset distribution. A straightforward optimization according to expression (1) calls for Clock Tree Synthesis (CTS)-like optimization algorithms. The main difference between CTS and reset tree synthesis is the lack of a low skew requirement, as long as constraint (1) is satisfied. Nevertheless, for an ASIC design, this approach results in a synthesis of a high-fanout net, consisting of a large number of large buffers. In an FPGA design, it results in employing multiple global net resources. The large capacitive networks pose an additional challenge of high switching current during reset toggling, requiring additional power resources. Taking into consideration that the asynchronous reset is little utilized – most often once per power up – the use of high fanout and global nets for it results in an unacceptable investment of power, ASIC area or FPGA routing resources, and EDA runtime.

The problem is exacerbated for large designs, where the reset synchronizer is clocked by a clock signal derived from the top of the clock tree, while the rest of the design is clocked by clock tree branches ‎[2]. In this situation, a precise post-layout STA, taking into account clock tree delays, is required to match the delay from the reset synchronizer to the rest of the logic.

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