Asynchronous reset synchronization and distribution – ASICs and FPGAs

August 04, 2017

dobkin-August 04, 2017

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs.

Asynchronous resets are traditionally employed in VLSI designs for bringing synchronous circuitry to a known state after power up. Asynchronous reset release operation must be coordinated with the synchronous logic clock signal to eliminate synchronization failures due to possible contention between the reset and the clock. A lack of such coordination leads to intermittent failures on power up. The problem exacerbates when large, multiple-clock domain designs are considered. In addition to the synchronization issues, the distribution of an asynchronous reset to millions of flip-flops is challenging, calling for techniques similar to CTS (Clock Tree Synthesis) and requiring similar area and routing resources.

The requirements and challenges of asynchronous reset are reviewed, focusing on synchronization and distribution issues. The drawbacks of classic solutions for reset synchronization (reset tree source synchronization) and distribution (reset tree synthesis) are discussed. Advanced solutions for faster and simpler timing convergence and more reliable reset synchronization and distribution are presented. Different approaches for ASIC versus FPGA designs are detailed.

Part 1 describes the issues surrounding asynchronous resets and outlines approaches for resolving those issues. Part 2 (this article) discusses additional solutions for correct asynchronous reset in ASIC and FPGA. Some useful special cases are discussed in Part 3.

2. Asynchronous reset timing convergence techniques

One of the main issues discussed in Part 1 was the complexity of reset release for large designs (with a high latency reset distribution network), especially when a short clock cycle is employed. The timing convergence based on standard STA optimization leads to an expensive design and in some cases is even impossible. Here we discuss two techniques that mitigate this timing issue. Both techniques are applicable for ASIC and for FPGA designs.

2.1. Asynchronous reset pipelining

One way to deal with the timing issue of asynchronous reset release is to trade off the reset release latency for a more relaxed timing. This can be achieved by pipelining the reset tree in the following way. After each synchronizer an additional asynchronous-set flip-flop stage P1 is included on the reset line (Figure 6a). Both SET and D inputs of the flip-flop are connected to the active high reset RSTO coming from the reset synchronizer. On the RSTO release, the setup and hold conditions are satisfied for P1 D and SET inputs since are constrained as a regular synchronous paths.

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Figure 6: Asynchronous reset with pipelining (Source: vSync Circuits)

The functional operation of the new scheme is similar to the regular one described in Part ‎1 (Figure 3d), except for an additional single cycle latency on the reset release. The higher reset latency incurred by this technique is usually acceptable for most applications, as it is incurred only once per power up.

A complementary part of this technique covers design constraints. While the synchronizer flip-flops must be constrained against duplication in order to prevent re-convergence path issues as described in Part ‎1, the pipeline stage P1 is subject to MAX_FANOUT constraining. An example of maximal fanout constraint is shown in Figure 6b. The P1 flip-flop is automatically duplicated by synthesis tool, creating four sub-networks for the reset distribution. Each sub-network has a lower latency than the original network, meeting the timing requirement for the reset release. In addition, the output of the reset synchronizer easily meets fanout of eight.

This asynchronous reset pipelining technique is scalable for any design size and requires no changes when the design is changing, as the synthesis tool duplicates automatically the P1 stage, keeping the moderate-latency reset sub-net bounded. The duplicated P1 stage fanout for synchronizer output is usually small and does not cause timing violations. However, when a single pipeline stage does not lead to timing convergence, additional pipeline stages P2 – PN can be included and constrained with different MAX_FANOUT constraints.

An example of this technique applied to a real design is shown in Figure 7. The P1 stage register, named PORT6, was automatically duplicated about 40 times by the synthesis tool ‎[6] to meet the MAX_FANOUT constraint. Each of the 40 sub-nets met timing for its local fanout.

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Figure 7: Example of asynchronous reset pipelining (Source: vSync Circuits)

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