Asynchronous reset synchronization and distribution – Special cases
Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs.
Asynchronous resets are traditionally employed in VLSI designs for bringing synchronous circuitry to a known state after power up. Asynchronous reset release operation must be coordinated with the synchronous logic clock signal to eliminate synchronization failures due to possible contention between the reset and the clock. A lack of such coordination leads to intermittent failures on power up. The problem exacerbates when large, multiple-clock domain designs are considered. In addition to the synchronization issues, the distribution of an asynchronous reset to millions of flip-flops is challenging, calling for techniques similar to CTS (Clock Tree Synthesis) and requiring similar area and routing resources.
The requirements and challenges of asynchronous reset are reviewed, focusing on synchronization and distribution issues. The drawbacks of classic solutions for reset synchronization (reset tree source synchronization) and distribution (reset tree synthesis) are discussed. Advanced solutions for faster and simpler timing convergence and more reliable reset synchronization and distribution are presented. Different approaches for ASIC versus FPGA designs are detailed.
Part 1 describes the issues surrounding asynchronous resets and outlines approaches for resolving those issues. Part 2 discusses additional solutions for correct asynchronous reset in ASIC and FPGA. Some useful special cases are discussed in Part 3 (this article).
3. Asynchronous reset special cases, tips and tricks
3.1. Asynchronous reset in FPGA – Power up initialization
FPGA vendors do not recommend using asynchronous resets for FPGA designs . In addition to the synchronous reset option, modern FPGA synthesis tools provide another initialization option as follows.
During FPGA programming process, each cell is initialized. This can serve as a global reset covering not just flip-flops but also other internal IP modules of FPGA, such as memories and DSP blocks . Note that resetting memories and DSP blocks by an asynchronous reset is not supported at all.
Such power up initialization can be safely employed for all FPGA flip-flops that do not belong to the following special categories:
Reset is functional during the application run, and not only at power up.
Reset value depends on an external pin value.
In many designs, the number of flip-flops that belong to the special categories above is very limited. For these flip-flops an asynchronous reset cannot be replaced by the power up initialization option, and the asynchronous reset synchronization schemes, discussed in Part. 2, should be employed. The rest of the design flip-flops can be reset at power up by the programming initialization option, which leads to a significant reduction of FPGA utilization .
A few examples of flip-flop initialization for VHDL and Verilog are shown in Figure 10. FPGA vendor synthesis tools support a few more coding styles in addition to those shown in the figure.
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Figure 10: FPGA power up initialization value example (Source: vSync Circuits)
Summarizing this section, it is important to emphasize that this technique is NOT suitable for an ASIC design.
3.2. Asynchronous reset de-bouncing
The asynchronous reset network must be kept clear of glitches and unintentional toggles to ensure correct operation. Unfortunately, asynchronous reset drivers can be noisy, calling for a special treatment inside the ASIC or FPGA. A few examples of noisy drivers include:
A noisy reset button, generating multiple toggles when pressed and released.
An inductive coupling between asynchronous reset board trace and other board traces . This one is extremely dangerous, as it can cause an unintentional full or partial design reset during normal operation.
In an environment exposed to radiation, a Single Event Transient (SET) may take place due to radiation, causing spurious glitches over on-chip interconnect .
Glitch filters are employed for de-bouncing of the signal. The filters can be either purely combinational or synchronous. In the reset tree, special asymmetric buffer cells can be employed, filtering the glitches at each stage with a minimal timing penalty on the de-assertion edge. The asymmetric buffers filter relatively small glitches (e.g., up to 100 ps for the 65nm node). To filter longer glitches, combinational filters are used, taking into account glitch polarity, as shown in Figure 11. Although combinational glitch filters can be built directly using gates (or provided as part of the library) in an ASIC, in an FPGA they are built using LUTs with a special constraining .
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Figure 11: Glitch Filters. (a) Active High glitch filter (b) Active Low glitch filter (Source: vSync Circuits)
In rad-hard designs, an asynchronous reset network must contain no inverters, but only (asymmetric) buffers with the glitch filters inside, in order to ensure that following a SET, an induced glitch is filtered out by the closest buffer that encounters the glitch. Otherwise the glitch could be amplified, possibly causing an unintentional reset. This, however, restricts designs that require both asynchronous active low and asynchronous active high resets (e.g., due to an integration of different third-party IP modules). In that case, two separate asynchronous reset and asynchronous set networks can be employed (Figure 12), spanning the two separate groups of modules. It is worth noting that the asynchronous reset synchronizer shown in Figure 12 must be constructed of rad-hard protected flip-flops to minimize a chance of an unintended reset assertion due to a Single Event Upset (SEU) event in the flip-flops.
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Figure 12: Separate asynchronous reset networks for active low and active high resets to prevent glitch propagation (Source: vSync Circuits)
A synchronous filter can provide longer filtering time (e.g., for manual button noise filtering). An example of a synchronous de-bouncer is shown in Figure 13. The filter requires a free running clock. It filters both negative and positive bouncing. The filter time is configurable using either a pipeline of flip-flops or a synchronous counter. The output of this filter is an input to an asynchronous reset synchronizer.
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Figure 13: De-bouncing synchronous filter (Source: vSync Circuits)