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Asynchronous reset synchronization and distribution – Special cases

August 11, 2017

dobkin-August 11, 2017

3.3. Asynchronous Reset of Multiple Clock Domains

In a multiple clock domain design, an asynchronous reset should be separately synchronized for each clock domain (Figure 14a). A design may have multiple asynchronous reset sources, such as external reset (possibly cleaned up from glitches by a bouncing filter as in section ‎3.2), internal controls (e.g. voltage domain status indication) and PLL lock conditions. All these mutually asynchronous indications may be combined to a single Reset Enable condition, as shown in Figure 14a.

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Figure 14: Reset Synchronization in Multiple-Clock Domain (MCD) design (Source: vSync Circuits)

Since each reset synchronizer incurs an additional non-deterministic synchronization delay, expressed in terms of the targeted clock domain cycles, the different clock domains may leave the reset state at arbitrary different times (Figure 14b). This creates a system level challenge, requiring a specific definition and management of the reset release sequence to ensure specific order for exiting reset. In the example of Figure 14, assuming that a CLK1 domain module sends data to a slower CLK2 domain module, the system may require that clock domain CLK2 reset is released before that of CLK1, to ensure that CLK2 domain module is ready to receive data when CLK2 domain module starts sending it. This can be achieved by adding RSTO_CLK2 to the CLK1 reset synchronizer reset conditions (dashed line in Figure 14a).

Considering the complexity of multiple clock domains, multiple reset conditions and multiple inter-clock reset dependencies, an IP-based management of the reset circuitry is preferred. An example of a generic multiple clock domain reset synchronizer generator is shown in Figure 15 ‎[5]. The generator customizes reset synchronizer IP cores. Each synchronized reset output of the module can depend on a custom combination of input conditions and on other reset outputs, enabling a multi-stage timed reset release sequence. An IP-based reset synchronization not only reduces design and verification time, but also allows an automatic generation and management of reset constraints for synthesis and P&R tools.

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Figure 15: Global reset management by vSync vReset module [5] (Source: vSync Circuits)

A special note should be made regarding PLL/DLL reset. The reset to PLL/DLL should be separate from the reset of the logic that is clocked by the PLL/DLL outputs. Figure 16a exemplifies a wrong reset design. The asynchronous reset is directly connected to both PLL and a Reset Synchronizer. When the external reset is active, depending on PLL implementation, the PLL may output either a "glitchy" clock or no clock at all at its CLKO port. Thus, if using a trailing-edge reset synchronizer (Figure 3a) or when both asynchronous reset edges are synchronized creating a completely synchronous reset, the reset synchronizer flip-flops stay uninitialized upon the external reset release. This leads to a synchronization failure. The vdd-based synchronizer of Figure 3c behaves better as its flip-flops are asynchronously reset. However, it still may malfunction if CLKO is still unstable for some time after the reset release.

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Figure 16: Reset Synchronization with a PLL. (a) WRONG Reset design: reset disappears before it is synchronized; (b) Vdd-based reset synchronization depends on clock stability (Source: vSync Circuits)

A more reliable approach is shown in Figure 16b and involves a LOCK indication from the PLL. The LOCK indication provides an asynchronous indication of the CLKO stability, thus enabling filtering out the CLKO unstable time period. The trailing-edge and synchronous reset synchronizers will still fail in this scheme for the same reason, as CLKO may only appear when LOCK is asserted. On the other hand, the vdd-based synchronizer works fine in this scheme and therefore it is the recommended one.

PLL lock indication may be unstable and can be asserted and de-asserted several times before PLL stabilization. Although the reset synchronizer of Figure 16b works functionally correctly under these conditions, to avoid multiple synchronized reset (RSTO) switchings, the Reset Synchronizer can be configured with a deeper synchronization chain (e.g., 3 stages instead of 2), providing the reset synchronous de-assertion only after PLL lock stabilization. Alternatively, a counter based delay of multiple cycles may be applied to the LOCK signal.

3.4. Asynchronous Reset CDC Verification

The complexity of modern ASIC and FPGA designs calls for an automatic verification of reset schemes employed inside the designs. Asynchronous reset paths are a special case of Clock Domain Crossings (CDC) and are treated by special algorithms of EDA CDC verification tools. The asynchronous reset verification includes an identification of reset distribution trees and an analysis of reset synchronization schemes applied. The analysis must take into account the reset connections to regular synchronous logic as well as the connections to black-box IP cores. In addition, the analysis should validate possible reconverging path problems leading to incorrect clock release sequences in between different reset domains. Special analysis is applied to verify that reset domain crossings (RDC) do not cause functional failures ‎[13].

An asynchronous reset may span an entire design, thus the number of asynchronous reset CDC paths may be of the order of the number of flip-flops in the design. To deal with such a high number of timing paths, EDA tools must be able to present the information in a concise way, enabling an efficient report analysis. An example of such report generation and analysis is shown in Figure 17, where reset distribution trees and their sources are automatically identified, and a condensed textual and visual report is generated leading to an efficient and fast design analysis ‎[5]. The verification process can be reinforced by an automatic solution generation for identified faulty asynchronous reset CDCs and by an automatic constraints generations for the CDCs ‎[5].

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Figure 17: Asynchronous reset verification by vSync vChecker EDA tool ‎[5] (Source: vSync Circuits)

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