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Asynchronous reset synchronization and distribution – Special cases

August 11, 2017

dobkin-August 11, 2017

3.5. Make your IP-design ready

Digital IP products are intended for embedding in different types of design and are required to support fast and reliable integration into customer SoCs. This calls for developing highly parameterized and generic IP designs that could easily fit into a customer echo-system, including support of customer clock and reset schemes, area and power budgets, custom technology libraries and DFT. The IP design must also allow verification inside a custom system verification environment.

A generic IP product should allow the user to customize the reset options, allowing the choice of an asynchronous reset, a synchronous reset or both. Missing support for one of the reset types may prohibit using the IP or require significant re-design. It is also recommended, from DFT perspective, to separate the asynchronous and synchronous resets in the IP core, driving them from two separate IP module ports. This enables full asynchronous reset controllability for DFT. Additional generic parameters for the logic can include reset polarity and clock enable logic (for automatic clock gating insertion).

A generic template for such an IP logic development is shown in Figure 18. The left-hand size shows a VHDL process template. It employs functions for enabling asynchronous reset, synchronous clear and data sampling. The functions themselves are controlled globally through constant values (customized settings) allowing to define the polarity (c_polarity_* constants) and the function existence itself (c_use_* constants). When a c_use_* constant is false, the corresponding logic is eliminated, removing either asynchronous reset, synchronous clear or preventing clock gating insertion for the entire IP module.

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Figure 18: A template for a generic IP development enabling asynchronous reset and synchronous clear (Source: vSync Circuits)

IP modules are mostly provided in encrypted form to protect the IP. This poses an additional limitation on multiple-clock domain IP integration and verification. While IP providers usually separate the technology dependent logic, such as memory blocks, from the IP core logic (Figure 19a), the synchronization circuits are typically kept within the encrypted logic. The inability to verify the IP synchronization logic along with the entire SoC can lead to synchronization failure of the entire design, as possible CDC reconvergence and RDC issues are not covered. It should be also noted that the synchronization logic is also a technology dependent logic as its reliability (MTBF) highly depends on a targeted technology node and operating conditions, and therefore it is better be configurable and accessible.

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Figure 19: An integration and verification friendly IP packaging (Source: vSync Circuits)

The aforementioned reasons lead us to a conclusion that all CDCs should be exported to an upper level of the IP design, just as it is done for memory blocks (Figure 19b). This will allow their customization for a targeted technology, including their replacement by dedicated synchronization cells from the technology library. Once the CDCs are provided as open code, they can be verified by static and dynamic approaches, including the verification of the asynchronous reset distribution and its compatibility with global SoC reset scheme.

Some cell libraries miss a flip-flop cell with asynchronous set, although a flip-flop with asynchronous reset is provided. A simple trick shown in Figure 20 can solve the problem. The option of Figure 20b, when possible, is better than the one of Figure 20a as it provides better timing and area. A considerate IP provider can include such an option in its IP or move out all the asynchronously set flip-flops to the open-code section.

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Figure 20: Building a flip-flop with asynchronous set based on an asynchronous reset flip-flop (Source: vSync Circuits)

Last but not least, a note regarding IP delivery: The documentation provided along with the IP module should include a precise clock domain association requirement for all the ports of the encrypted IP. In some cases, the clock domain association varies dependent on the customization or on the operation mode. All these should be precisely reflected in the documentation. Such description is essential to verify that the IP module is correctly integrated inside a SoC design.

Conclusions

This paper surveys multiple issues related to asynchronous reset employment and distribution. We describe several techniques for dealing with high fanout reset distribution networks, minimizing or completely eliminating the timing issues, reducing area and design effort. Additional topics include the treatment of asynchronous reset in FPGA, de-bouncing, assuring reset in multiple-clock domain designs and verification of designs using asynchronous reset. We also share our view of desirable IP module packaging that allows reliable integration of the IP module in a SoC that employs asynchronous reset.

The enormous number of CDC paths in modern design, including asynchronous reset paths, calls for an automatic EDA approach for dealing with both integration and verification of such complex systems. Through the text, we provide a few examples of industrial tools that deal with such complexity, leading to high reliability products.

References

  1. G. Wirth, F. L. Kastensmidt and I. Ribeiro, "Single Event Transients in Logic Circuits - Load and Propagation Induced Pulse Broadening," IEEE Transactions on Nuclear Science, 55(6), 2928 - 2935, 2008.

  2. C. E. Cummings, D. Mills and S. Golson, Asynchronous & Synchronous Reset Design Techniques - Part Deux, SNUG, 2003.

  3. W. J. Dally and J. W. Poulton, Digital System, Engineering (Eds.). Cambridge University Press (1998).

  4. C. Dike and E. Burton, "Miller and noise effects in a synchronizing flip-flop," IEEE Journal of Solid-State Circuits, 34(6), 849-855, 1999.

  5. vSync Circuits Vincent Platform, http://vsyncc.com/products

  6. Altera, Quartus-II, www.altera.com

  7. Quartus II Handbook Volume 1: Design and Synthesis, pp. 11-19 – 11-29, 2014.12.15

  8. K. Chapman, "Get Smart About Reset: Think Local, Not Global", Xilinx, WP272 (v1.0.1), 2008.

  9. K. Chapman, "Get your Priorities Right – Make your Design Up to 50% Smaller," WP275 (v1.0.1), 2007.

  10. K. Chapman, "Xilinx-Ken Chapman-That Dangerous Asynchronous Reset!-External Antenna - Need for de-bouncer", PLD Blog, 2008.

  11. Xilinx, XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices, UG687 (v 13.1), pp. 50, 95, 128, 2011.

  12. Yaniv Halmut, RESET architecture in Altera FPGAs: utilization effects, private communication, RAD, 2016.

  13. Chris Kwok, Priya Viswanathan and Ping Yeung, "Addressing the Challenges of Reset Verification in SoC Designs", DVCon, 2015.


Rostislav (Reuven) Dobkin received PhD degree in electrical engineering from Technion, Israel Institute of Technology. Reuven is a co-founder and CTO of vSync Circuits LTD. (2010), a VLSI CAD company. In parallel, Reuven serves as a lecturer in Technion. Reuven has held management positions in radiation-hardened VLSI technology for space applications, in communications chip development, and in research in C4I systems, signal processing, software systems engineering and VLSI. Reuven serves as a reviewer of numerous VLSI journals and conferences. His research interests are VLSI architectures, asynchronous logic, synchronization, GALS systems, SoC, NoC, many-core processors and parallel architectures.

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