Using customizable MCUs to bridge the gap between dedicated SoC ASSPs, ASICs and FPGAs: Part 1
A new approach: metal
A new technology, called Metal Programmable Cell Fabric (MPCF), makes it possible to develop ARM-based structured ASICs, with routed gate densities and unit costs that are nearly identical to those of standard cells in the same process.
A metal programmable cell fabric library is custom designed and contains over 400 cells. It has an 8 transistor core cell that is only 3.2 um high and 2.0 um wide, and it uses 2 layers of metal for interconnect. Normally, a sea-of-gates design approach gives about 75% transistor utilization in placed cells plus a 70% placement utilization yielding a design that is just over 50% routable.
Based on these assumptions at 130 nm, the achievable gate density would be 156K gates per mm2. However due to its efficient cell routing and additional metal layers available at 130 nm, ASICs using the MPCF are achieving 80 to 90% placement utilization allowing gate densities on silicon of between 170K and 210K gates/mm2.
Show in Figure 3, below is the comparison of a MPCF cell implementing a D flip-flop (DFF) versus a standard cell DFF both in a 130 nm process. Despite the difference in aspect ratios, the two flip-flops consume nearly the identical area. Actually, the standard cell DFF is larger and consumes 1.07 times more area than the MPCF DFF, which uses two stacked metal programmable core cells.
|Figure 3: D-type Flip-flop in 130 nm MPCF and 130 nm Standard Cell|
As one can imagine, given this cell comparison, the routing density for the MPCF library is essentially the same as the standard cell routing density at 130 nm. In fact, routing studies show that there is more variation in routing density from design to design than from standard cell to MPCF.
In addition, the speed performance of the MPCF also appears to be nearly equal to that of the standard cells. However as might be expected, the MPCF cells do consume 10 to 15% more current than the standard cells in the same process technology.
Metal-programmable cells and standard cells can be placed in separate regions on the die or freely mixed without any die size penalty. In fact, a variant metal programmable cell was created for the MPCF with the same cell height, 3.6um, and aspect ratio as the standard cells to allow these cells to be placed in empty locations within a standard cell region of the die.
These filler cells take-up no extra silicon space and they are initially programmed as a decoupling capacitor. If an engineering change is required, any new logic can be implemented using these metal programmable filler cells.
Given this design approach, engineering change orders (ECO's) are much easier to route than with the traditional method of using a cluster of spare cells because the filler cells are more evenly distributed and can be made to implement any logic function required.
As a result, more complicated ECO's that affect over 10% of the logic can be successfully routed whereas a conventional flow using spare cells can only accommodate ECO's that affect up to 1% of the logic.
The MPCF can be integrated with a variety of microprocessor cores, most commonly ARM7 and ARM9; DSP cores, digital IP blocks, analog cells, and I/O and package options. The same design tools from Cadence, Mentor Graphics, and Synopsys as are used for standard cell ASIC design can be used to design with the MPCF.
Since the overall platform cost is lower with MPCF ASICs, multiple and very low-cost derivatives ($30K to $100K) can be developed for target specific markets including automotive, embedded displays, military and industrial control systems and utility meters. This is also an ideal platform methodology for fabless semiconductor companies that need to create a new product line (Figure 4, below).
|Figure 4. FPGA vs ASIC costs|
Using this technology, fabless semiconductor companies can develop custom ARM-based platforms that are prototyped using an off-the-shelf ARM microcontroller and an FPGA.
Like any conventional ARM-plus-FPGA design, the prototype design can be used for production while volumes are low. Once market acceptance is verified, the prototype can then be migrated it to an ARM-based MPCF platform with quick turn-around, low NREs and with unit costs that approach those of standard cell ASICs.
Customers can develop proprietary ARM-based MPCF platforms that allow their products to efficiently evolve with new functions or features as their markets change. Consider the metrics shown in Figure 5, below.
|Figure 5. Block diagram of an ARM-based MPCF SoC|
With an MPCF platform, the customer decides exactly what is in the chip, including the right peripheral set, memories and matching the right gate count for their custom IP. With NREs of as low as $150,000, and unit prices close to those of cell-based devices, an MPCF platform is cost-effective at volumes as low as 25,000 units.
Another important consideration is migration from a standard product. MPCF platforms can be modeled after ARM-based standard products now available on the market. The ARM-core platform, is already qualified in silicon via the standard product. Not only does this reduce the risk, but also offers a seamless migration path from these standard off-the-shelf ARM products to a cost effective custom solution.
The design used to test the market and garner market share can be directly ported to the MPCF-based platform ASIC. Moving the ARM core, AMBA bus and peripherals into a SoC and converting the IP in the FPGA to a cost effective one-chip solution becomes a much easier path. The effective end result is the right combination of NRE, unit price and ease of use.
Existing, low cost ARM7 and ARM9 hardware development platforms allow software to be co-developed with seamless migration to an MCPF ASIC. Power consumption of an MPCF-based structured ASIC will be very close to that of a stand-alone MCU without an ASIC - roughly 10mA static for an ARM9-based SOC.
This is two orders of magnitude less than the 1900 mA consumed by and FPGA. Since the logic that was in the FPGA is programmed in the metal fabric of the MPCF-based ASIC, it is immune to software pirating.
There is no need to develop an ASIC-style design methodology because an MPCF ASIC can be easily migrated directly from standard products. The MPCF platform can retain much of the flexibility of its FPGA-prototype, while offering unit prices comparable to those of cell-based ASICs, even at relatively low volumes. As a result, we may expect to see renewed growth in the structured ASIC market.
Next in Part 2: Building a MPCF/MCU-based custom SoC
Jay Johnson is ASIC Marketing
Director at Atmel