Debugging with Cortex-M3 Microcontrollers

Reinhard Keil, Arm Ltd.

July 22, 2008

Reinhard Keil, Arm Ltd.July 22, 2008

Before the introduction of on-chip debugging, most software developers were using expensive In-Circuit Emulators (ICE) for application testing on microcontrollers.High-end emulators were connected via complex adapters, and offered also extensive instruction and data trace capabilities with complex triggers.

These emulators were based on special bond-out devices that were different from the standard production devices and therefore very expensive compared to the actual MCU device.

Modern microcontrollers run at high clock rates and come in tiny, high-pin count packages making traditional ICE technology impossible to adapt. Today's microcontrollers offer on-chip debug logic that gives controlled access to memory, CPU registers, and program execution.

This on-chip debug logic is part of every production device and, to avoid extra chip costs, is limited in complexity. Since it is mostly accessed using a standard JTAG interface, the additional bandwidth required for instruction trace is not available.

Most on-chip debug implementations provide only simple run-control debugging with limited breakpoint features. Cortex-M3 processor-based microcontrollers, however, integrate ARM CoreSight debug technology that provides useful trace information via a standard JTAG connector and without the need for costly hardware.

ARM On-Chip Debug Technology
With the introduction of the ARM7TDMI processor ARM provided the on-chip Embedded ICE debug solution. Embedded ICE is a low-cost hardware block that provides complete run-control with two hardware break registers that can trigger either on program execution or memory access.

An additional Debug Communication Channel (DCC) allows data exchange with the user application during program execution. The Embedded ICE is the standard debug unit for all ARM7 and ARM9 processor-based microcontrollers that are available today from many silicon vendors. It is widely supported by the tools industry with standard low-cost JTAG interfaces that eliminate the need for costly hardware adaptations.

Since the Embedded ICE on-chip debug hardware does not provide any data or instruction trace, some ARM processor-based microcontrollers also integrate the Embedded Trace Macrocell (ETM).

However the high data bandwidth used by an instruction trace requires data output lines, in addition to those of the standard JTAG pins. A special ETM emulator connects to these ETM data output lines and interprets the trace information.

In microcontrollers, ETM often shares useful I/O lines that are required by the user application and therefore engineers frequently cannot use the ETM unit. To minimize the I/O pins required for debugging, the new CoreSight solution provides additional operating modes via a standard JTAG connector:

1) A standard JTAG mode using five I/O pins for the connection to a JTAG chain or legacy JTAG adapters.

2) A Serial Wire (SW) mode that requires only two I/O pins for run-control debugging. The SW mode is a different mode of the JTAG port that requires only the pins TCLK and TDI for communication.

3) When working with the SW mode, an additional Serial Wire Viewer (SWV) output on the TDO line can provide data trace, event trace, and instrumentation trace information.

Table 1: Comparison of Debug Features

CoreSight is the debug technology used in Cortex-M3 processor-based microcontrollers. A low-cost JTAG adapter (for example the Keil ULINK2) is all that is required to interface to the CoreSight on-chip debug unit.

In addition to the trace features, the CoreSight unit implements additional break registers and provides on-the-fly memory access during program execution without additional software overhead.

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