Advertisement

Building advanced Cortex-M3 applications

Jean J Labrosse, Lotta Frimanson and Anders Lundgren

October 29, 2009

Jean J Labrosse, Lotta Frimanson and Anders LundgrenOctober 29, 2009

The ARM Cortex-M3 architecture provides many improvements compared with its predecessor, the popular ARM7/9, and is designed to be particularly suitable for cost-sensitive embedded applications that require deterministic system behavior.

It's a member of the Cortex-M family, one of the three ARM Cortex architectures that were introduced to the embedded marketplace in 2004, and is being integrated into low-cost embedded microcontrollers (MCUs) from an increasing number of silicon vendors.

A comparison of the main characteristics of Cortex-M3 with those of ARM7/9 is shown in Table 1 below. The Cortex-M3 improves on the ARM7/9 in most qualitative estimates " simpler stack architecture, better interrupt controller, and higher-performance instruction set, as well as enhanced debug capabilities, all of which can significantly affect end-product performance.

Table 1. Comparison of Cortex-M3 and ARM7/9

Stacking and Interrupts
The Cortex-M3 reduces both the overhead and complexity of ARM7/9 stack management by incorporating only two stacks. Tasks execute in Thread mode, using the process stack, while interrupts execute in Handler mode, using the main stack.

The task context is automatically saved on the process stack when an exception occurs, upon which the processor moves to Handler mode, making the main stack active. On return from the exception, the task context is restored and Thread mode re-instated if the interrupted task remains the active task.

If, however, a new task is to be scheduled, the context switch must take place(Figure 1 below. Because the task context is already saved, this procedure is more straightforward with the Cortex-M3 and also consumes 50% fewer processor cycles.

Figure 1.Cortex-M3 Task Switching

Migration between processors
The Cortex-M3 includes several integrated peripherals in addition to the core CPU. Most important of these is the Nested Vectored Interrupt Controller (NVIC), designed for low latency, efficiency and configurability.

The NVIC saves half the processor registers automatically upon interrupt, restoring them upon exit, allowing for efficient interrupt handling. It also removes the need for saving/restoring registers during back-to-back interrupts. The NVIC also integrates the SysTick, a 24-bit down-counting timer intended for RTOS use.

The NVIC and SysTick peripherals ease the migration between Cortex-M3 processors, particularly when an RTOS is used, as it simply requires a function that returns the clock frequency on which the SysTick timer is based.

In contrast, an RTOS port to an ARM7TDMI-S processor would require a port to the interrupt controller of the processor and a port to a hardware timer in addition to the generic ARM port. The interrupt functionality, which must be written individually for each ARM7/9 port, is provided just once for all Cortex-M3 implementations.

The sleep mode feature of the Cortex-M3 can be used to conserve power when the target application is idle. For example, with C/OS-II the idle task calls an application-level hook that causes the processor to enter sleep mode until the next interrupt is received. Unlike most previous ARM processors, the Cortex-M3 also has a fixed memory map.

< Previous
Page 1 of 3
Next >

Loading comments...

Most Commented