Programming heterogeneous multicore embedded SoCs
Over the last decade, the market demand for increased processing performance with reduced power and area footprint has remained strong and embedded SoCs have stepped up to the challenge. This performance, power and area (PPA) improvement has been achieved by adding cores – both general purpose cores and specialized cores such as DSPs and GPUs among other things. This trend has resulted in networks of heterogeneous multicore embedded SoCs. An example of this trend is shown in Figure 1.
Traditional approaches to programming such complex SoCs focus on manually partitioning the application across the various cores and hand optimizing the appropriate sections of the application for a given core. This approach tends to yield the maximum entitlement but has the following drawbacks:
- The partitioning is static and has to be redone for each system configuration.
- Increased time to market because programmers need to develop their own dispatch, communication and synchronization mechanisms
- The resulting application is not portable
- Requires detailed knowledge of the SoC and network architecture
- Make modeling “what-if” scenarios difficult because significant rework is required to move a section of the application that has been mapped and optimized for one type core to another core
An important observation is that as embedded SoCs increase in complexity, they are starting to look a lot like their desktop counterparts from a software architecture standpoint. A typical high-performance heterogeneous embedded SoC consists of the building blocks shown in Figure 2.
Figure 2 : TI 66AK2H - Sample end equipment
This leads to the following question: Can we re-use traditional multicore programming paradigms such as OpenCL, OpenMP and MPI in the embedded space? The remainder of the article focuses on answering this question by using the TI 66AK2H SoC as a case study.
The main compute cores are an ARM MPCore cluster with 4 Cortex-A15s (host) and a DSP cluster with 8 C66x DSP cores (accelerator). The host and accelerator share on chip and off chip memory. The 66AK2H is used in end equipment ranging from single SoC systems to multiple networked SoCs. Figure 3 is an overview of standard multicore programming models layered on the 66AK2H. Programming models above ARM MPCore are used to program the ARM cluster. Models that span both ARM & DSP are used to dispatch from ARM to DSP.
- OpenMP and/or OpenCL can be used to:
- Dispatch code/data from the host to the accelerator
- Parallelize applications across the ARM MPCore cluster
- Parallelize regions of the application dispatched to the DSP cluster
- Across multiple SoCs, MPI is used to partition the application and manage program execution, data transfer and synchronization
Figure 3: Tooling for 66AK2H
Dispatching to the DSP cluster
Both OpenCL and OpenMP 4.0 (Accelerator model) can be used to offload compute intensive portions of an embedded application to the accelerator.
The above code snippet is an example of dispatching an OpenMP parallel region using the target construct. The map clauses on the construct indicate data movement required before and after executing the dispatched region.
The above code is a similar example with OpenCL using the C++ bindings for OpenCL APIs
Using a standard programming model or API allows the programmer to quickly handle the mechanics of dispatching code and data from the host to the accelerator and focus on optimizing code for the system. The programmer can also leverage tooling (debuggers, profilers) & training ecosystems built around these standard programming models.