A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies
Editor’s note: This work was first presented at the 2011 IEEE International Electron Devices Meeting (IEDM) and appears here courtesy of the IEEE. For more information about IEDM 2012 (San Francisco, CA; December 10-12), click here.
A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) Quad spacer patterning technology (QSPT) of ArF immersion lithography is used for patterning mid-1x-nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x-nm design rule NAND flash memories has been successfully realized.
The NAND flash memory cell has been scaled down to the 2x [1,2,3] and 2y nm  generations aggressively. As scaling down of a cell size, many serious scaling problems were caused in 2x and 2y nm generation, however they were solved or managed by process, device, and system solutions. For further scaling down beyond 2y nm, we face new scaling limitations such as patterning limitation of ArF immersion spacer patterning technology (SPT), more severe control gate (CG) poly-Si filling problems between floating gates (FGs), and high electric field and charge loss problem between WLs. This paper describes several new advanced processes and operation schemes to overcome these problems, as shown in Table 1. As a result, M1XNAND flash cell is successfully implemented with highly manufacturable integration technologies.
M1X-NAND cell process
Figure 1 shows the layout of M1X-NAND flash cells. The half pitch of WL is middle-1x nm. The BL contacts are formed staggered arrangement and a string has several dummy WLs. In order to pattern middle-1x nm design rule WLs, QSPT is intensively developed to overcome limitation of ArF immersion SPT.
As shown in Figure 2, first patterns are formed by photolithography and the two times combination of previous formed pattern and spacer are formed final patterns.
The WL critical dimension (CD) of QSPT, which plays a very important role of Vth distribution factor, is precisely controlled less than 1.5% uniformity (see figure 3). QSPT is successfully adopted for mid-1x-nm design rule NAND cell patterning.
Figure 4 shows cross-sectional TEM micrographs of M1X-NAND cell, (a) along WL-direction, and (b) along BL-direction.
The floating gate slimming process can achieve the void-free filling of CG poly-Si and wider active area CD, which can obtain large cell current. An electrical depletion in CG poly-Si is greatly suppressed by this void-free process. As a result, BL interference is successfully improved 20% compared with conventional process (see figure 5). The CG CoSi height was selected reasonably to achieve optimized gate shape and decrease WL RC delay for improvement program performance.