Solving power management of multiprocessor systems with the eXtensible Energy Management Interface

Davorin Mista, Vojin Zivojnovic, Soren Brinkmann, Zach Pfeffer

December 08, 2015

Davorin Mista, Vojin Zivojnovic, Soren Brinkmann, Zach PfefferDecember 08, 2015

Multiprocessing is ubiquitous in today’s electronic systems. The key benefits are faster processing due to parallel execution and improved operating characteristics such as power, thermal and latency by engaging the right processor(s) for each activity. The same is valid for multicore systems that typically have even closer data and timing ties between the processing units.

Historically, parallel execution and the resulting performance gains have received most of the attention of the engineering community which produced progressive parallel software standards such as Open Computing Language (OpenCL), Heterogeneous System Architecture (HSA), Open Multi-Processing (OpenMP) and similar. The operating characteristics of multiprocessor systems, like power, although vital for electronic systems, stayed entrapped in the OS-directed power management (OSPM) bundled with the main OS as the exclusive controller of the whole system. The first challenge to OSPM came with multiple guest OSs running on a single processor hypervisor, followed by the multi-OS, multicore hypervisor variant and finally the heterogeneous multi-OS, multiprocessor systems. Consequently, hypervisors and dedicated cores started taking over the OSPM role, and engineers developed homegrown power APIs to coordinate power control between various OSs of the electronic system.    

The Latency/Power Tradeoff Problem
There is currently no commonly used standard to manage system power in heterogeneous multiprocessor systems. Each vendor must reinvent APIs and protocols to handle power management and spend time integrating these APIs into each codebase for every processing core in the system. To meet market windows, vendors tend to leverage existing power management solutions in the software they use for each core and then loosely couple these cores together to create ad hoc power-management regimes. These ad hoc regimes tend to have high latency power-state transitions. To work around this, companies create static, infrequently updated data-driven approaches, trading off latency for power. Because of these tradeoffs, vendors have to leave power on the table.

New Power API for Heterogeneous Processors
A solution to this problem is to create an API specification that all software vendors can reasonably implement, a spec that acts as an underlying power management substrate. Because of the unique needs of heterogeneous systems, it should be possible to implement the API using a small amount of code so that even the smallest cores can participate in system-wide power management. The API should also be sufficiently generic so that most heterogeneous architectures can be represented, but not too generic that the API becomes hard to use. Finally, the API should be compatible with existing power management schemes like ARM’s Power State Coordination Interface (PSCI).

The new eXtensible Energy Management Interface (XEMI) developed by AGGIOS and Xilinx over the last two years fulfills each of these requirements.

XEMI is not revolutionary; it is not intended to be. XEMI is similar to ARM’s PSCI. Unlike PSCI, XEMI covers heterogeneous systems. XEMI's intention is to provide a common API that allows all software components to power manage cores and peripherals. At a high-level, XEMI allows the user to specify a high-level power management goal such as suspending a complex processor cluster or just a single core. The underlying implementation is then free to implement an optimal power-saving approach autonomously. This approach cuts latency because the requestor of the action can specify a high-level power goal and not have to execute each step of the power state transition.

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