Balancing memory performance and power consumption in IoT applications

July 03, 2017

reubenbenjamin-July 03, 2017

Considering the above factors, SRAMs have tried over the years to balance the trade-off between fast and low power products. One of those solutions is a hybrid device that falls midway between fast and low-power in both access time and power consumption. However, these hybrid SRAMs are unable to meet the performance requirements expected from Fast SRAMs. The best approach is a Fast SRAM with on-chip power management, ensuring both high-performance and low-power.

SRAMs with on-chip power management work in a similar way as MCUs with on-chip power management. In addition to active and standby modes of operation, there is a deep sleep mode of operation. Such a setup allows the SRAM to access data at full speed during its standard mode of operation. During the deep sleep mode of operation, the device doesn’t perform any functions and so can keep current consumption extremely low, on the order of 1000 times less than the standard standby consumption of Fast SRAMs.Table 1 shows a comparison of power and access time for the two common types of SRAMs – Fast and low power – as well as Fast SRAM with Deep-Sleep.

Table 1: Comparison of different types of SRAM (Source: Cypress)

The numbers clearly demonstrate the advantage of using a “Fast with Deep Sleep” SRAM over a standard Fast SRAM. This advantage will be more prominent in applications where the SRAM is in standby mode most the time.

In many latest generation battery-powered systems, getting to the sweet spot for memory power consumption is a fine balance of time needed to store the data and power consumption during the process. For example, consider an application that needs to write 100 Kb of data every 1 millisecond. If we are to use a Fast SRAM, it takes 10ns to write 2 bytes of data. Thus, a Fast SRAM will have a 6% duty cycle, which translates to 130 Watt-Hour (WH) over 1000 hours of operation. By contrast, a low power SRAM required to do the same task will have a 31% duty cycle, consuming much less power at 2WH. However, the SRAM isn’t the only component that’s awake while the SRAM is being written to. When factoring the MCU’s power consumption in, the ratio could skew in favor of Fast SRAMs.

A Fast SRAM with Deep Sleep completely eliminates the need to evaluate this trade off. With the duty cycle of a Fast SRAM and the standby current of a Low-Power SRAM, these SRAM consume significantly lower power than Fast SRAM with a much shorter duty cycle than low power SRAMs. This means the MCU is required to stay active for a shorter time while writing data to the SRAM. For battery-powered systems, the overall drop in system power due to the lower duty cycle of Fast SRAM with Deep-Sleep can be quite significant. Table 2 shows the results of battery-powered tests we conducted at Cypress. The shorter duty cycle is due to Deep Sleep extending battery life by around 20% compared to systems that use a low power SRAM instead.

Table 2. A comparison of SRAM power consumption (in WH) by the three types of SRAM for a sampling of duty cycles. (Source: Cypress)

There is an important factor to consider when using deep-sleep mode (be it MCU or SRAM) - time taken to enter and exit deep-sleep mode. If the time interval between two active periods is too short in comparison to the time taken by the SRAM to enter or come out of deep-sleep mode, then the method will not be useful. This could potentially be the biggest hurdle to the widespread adoption of SRAMs with deep-sleep mode. In the case of Cypress’ Fast SRAMs with Deep-Sleep, this figure is 300µs (max).

A common concern, especially in battery-backed systems, is that a new feature like deep sleep will require extensive redesign. This is not the case when transitioning a standard battery-backed system that uses a supervisor chip. In a standard battery-backed system, the address lines, data lines, and control signals are driven by the processor. However, the active low chip enable of the SRAM is driven by the supervisor chip, which adds no significant overhead during normal operations. During power failure, the supervisor chip seamlessly switches from the board power supply to the battery supply and disables the SRAM, thereby preventing data loss.

This same system can be easily migrated to Fast SRAM with Deep-Sleep capability. To use the deep sleep functionality, there is a special pin (DS), which is toggled active low to enter deep-sleep mode. The equivalent pin on a standard Fast SRAM happens to be NC (no-connect). Thus, upgrading from a standard Fast SRAM to a Fast SRAM with deep sleep requires minimal design effort (one extra pin has to be interfaced).

During normal operation, the SRAM can be operated at fast speeds. During a power failure, the SRAM can be automatically switched to deep sleep mode by asserting the deep sleep signal. When the power fails, the supervisor chip disables the SRAM and pulls down the deep sleep pin, which will automatically switches the SRAM into deep sleep mode. Once the processor has booted, the deep sleep pin is switched high to restore the SRAM into a standard high speed SRAM. The application note Power Saving SRAMs outlines the implementation of such a switch and explains the critical timing considerations that need to be managed by the supervisor chip during power failure events.

Reuben George works in Product Marketing for the Memory Products Division at Cypress Semiconductor. He holds a BE in Electrical & Electronics Engineering from the prestigious Birla Institute of Technology and Science (BITS), Pilani in Rajasthan, India.

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