Reducing MCU power consumption without compromising response times

October 29, 2017

luciodj-October 29, 2017

Editor's Note: The ability to operate an MCU's peripherals independently from the core provides a powerful capability for embedded systems engineers. Developers can keep the MCU core in a low-power state while relying on MCU peripherals to respond to external events without involving the core. To help engineers use these techniques, Lucio Di Jasio provides background on MCU features and core independent peripherals, offering examples illustrating their use in his book, This is (not) Rocket Science. In this excerpt from the book, the author describes the use of low-power modes and their use with core independent peripherals. 

Adapted from This is (not) Rocket Science, by Lucio Di Jasio, available from online booksellers including Amazon, Barnes & Noble, and Lulu.


Chapter 9. XLP – eXtreme Low Power

As 8-bit PIC® microcontrollers have become ever more capable, their power consumption has been squeezed to extreme levels. While not all applications need to operate from a battery for a decade straight as some marketing types would like you to believe, there are many advantages that can come from a more conservative use of energy. Smaller power supply circuits, less noise, less heat and hence smaller packages, and in general a small application form factor are all desirable features.

About a decade ago all PIC microcontroller designers committed to a common set of power consumption target figures called the eXtreme Low Power (XLP) standard. The original set included an ambitious maximum current consumption of the device when in Sleep (lowest-power mode) of 100 nA (that is nano Amperes!) But also the Watchdog and the Secondary Oscillator (SOSC) had a target of just 800nA each.

Today, all PIC16F1 devices routinely pass those criteria and by a wide margin.

In fact it is common to find on the device datasheet values that are almost an order of magnitude lower: 20nA in Sleep and less than 300nA for WDT and SOSC. Even the dynamic power consumption of the microcontroller, that is the current consumption when actually executing the application, has been similarly reduced by orders of magnitude with current values commonly in the 30 uA/MHz (micro Ampere per MHz of system clock).

These are values that would be very hard (if not impossible) to achieve with larger (16 and 32-bit) architectures because they require the use of much smaller, and therefore leaky, CMOS processes. In fact it is common for those architectures to adopt radical expedients (deep sleep modes) just to get near much less ambitious figures (few micro Amperes) at the cost of RAM contents loss and lengthy wake up times. None of that is necessary with the PIC16F1 microcontrollers as even when in the lowest-power mode they do preserve the full contents of the RAM memory and yet can wake up in microseconds.

Low Power Modes


Sleep has been the signature low power mode of all PIC microcontrollers from the beginning of time. Initially it was used to indicate a mode where the main system clock is stopped and with it pretty much any activity of the microcontroller save for the Watchdog timer thanks to its independent oscillator.

In the PIC16F1 generation of devices though, the list of independent oscillators available on chip has grown considerably and with it the number of possibilities. Sleep still means stopping the system clock, and therefore the core instruction execution, but many peripherals are capable of continuing their operation if configured to use the alternate oscillators. Examples of such peripherals include:

  • Timer1, a 16-bit timer, when using the Secondary Oscillator (SOSC) or when used as a counter in asynchronous mode.

  • Analog-to-Digital Converter (ADC), when using the dedicated internal oscillator (FRC)

  • All core independent peripherals when using directly one of the oscillators (for example HFIntOsc instead of Fosc/4).

Low Power Sleep

The low-power sleep feature must not be confused with the deep sleep mode of other architectures. It applies only to PIC16F1 devices that operate at 5V and therefore using the internal LDO. Such LDO can be switched to a lower power mode (with resulting lower quiescent current) when selecting the low power feature. Note that RAM contents integrity is fully preserved, but wake up time is affected as the return to full power requires a short stabilization delay.


There are several events that can force the microcontroller to exit the low power state and resume operation, including:

  • External Reset (MCLR)

  • BOR reset

  • Watchdog timer

  • Any external interrupt

  • Any interrupt produced by a peripheral that is operating asynchronously with the system clock

Regardless of the trigger event, waking up from sleep, the MCU will continue executing the instruction immediately following in program memory.

This is true even for peripherals that would otherwise generate an interrupt if the interrupt enable bit is cleared (not enabled).


Idle mode was introduced first in PIC18 models and more recently in PIC16F1 models (such as the PIC16F183xx and PIC16F188xx families) to allow the microcontroller to stop executing while keeping all other clock systems up and running, including those peripherals that are configured to operate off the system clock. The power savings achievable is noticeable but not remotely comparable to the savings achieved by Sleep mode.


Doze mode was similarly introduced in the most recent PIC16F1 families to further increase the granularity of power consumption control. When in Doze mode the core is allowed to continue to run although its clock source is divided further by a factor that can be selected between 1:2 to 1:256.

The result is once more a power consumption reduction proportional to the scaling factor chosen, with the benefit of allowing all peripherals to continue operating as well as some (reduced) core activity.

Doze Interrupt Boost

When in Doze mode, it is possible to configure the device so that an incoming interrupt will make the core return instantaneously to full speed. It is possible then to ensure that the core will return to doze mode upon interrupt exit. Effectively the combination of the two options can be used to produce a sort of interrupt boost. In other words, it is possible to conceive low power application where the main application loop is normally executed at a desired fraction of the clock (i.e. 1:8 = 4MHz) and only interrupt routines get to use the full speed and maximum performance the microcontroller is capable of (1:1 = 32MHz).

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