Optimizing wearable display power consumption
Long battery life is crucial to a positive user experience in wearable devices. Research shows that the most battery power in a wearable application is consumed by the display. One approach is simply to increase battery capacity, but the required size and weight of larger batteries is not practical in wearable devices, especially as the market expands to new, smaller form factors. Increasing the challenge, advances in battery technology are not keeping up with increasing system demands. Therefore, minimizing display power consumption is a key design consideration for the wearables market.
Human visual perception is quite precise, driving the trend towards higher resolution displays in wearable devices. Various energy conservation schemes can be implemented, but any degradation in visual quality will directly affect the overall experience with the device. Therefore, care should be taken when considering energy conservation schemes for displays. Higher resolution displays require high memory bandwidth, so reducing memory power consumption in both standby and active modes is required to improve battery life.
Display system architecture
Displays consist of an array of pixels. Values driven to each pixel determine the color displayed. A RAM-based frame buffer holds the color information of each pixel in the display. Most common parallel displays require refresh cycles which read data from the frame buffer then display it on the LCD. If the resolution and color depth of the display is low, the controller’s internal RAM can be used as the frame buffer.
As displays get larger, with greater resolutions and color depths, internal RAM will not provide sufficient size or performance. Double buffering will also be required to avoid the risk of screen tearing. In these systems, it’s common to implement the frame buffer in an external memory. During the refresh cycle, data is read from the external frame buffer and output to the LCD controller data bus along with control signals. Figure 1 shows a typical LCD display with an external frame buffer.
Figure 1. Parallel SRAM display buffer implementation (Source: Cypress)
There are several ways to reduce display power.
Integrate the display controller inside the main microcontroller. Commonly available display modules have a built-in controller. Having the display controller as part of the main microcontroller helps to utilize low power features of the main microcontroller.
Use low power memory as a frame buffer. Since the frame buffer is always on, it is important to have a memory with low standby current.
Reduce frequent updates to the frame buffer. Having a sufficiently large memory and having multiple frames loaded reduces the CPU active current. If the most frequently accessed frames are loaded into memory, there is no need to load and unload data from the frame buffer. Switching the frame buffer to a different memory location can switch the images on displays.
Traditionally, Parallel Asynchronous SRAMs have been used as external display buffers since they have been readily supported by the controllers and displays. However, these memories require large packages with high pin counts. Alternatively, serial memories reduce pin count and package size, which reduce required controller pins and saves PCB cost. While operating at 108MHz in Quad SPI mode, a serial memory can meet the performance of Parallel Asynchronous SRAMs. For example, the Cypress Excelon F-RAM is a serial non‑volatile memory up to 8 Mbit density available in low pin count, small GQFN packages. The device supports four power modes to optimize power consumption. Typically, 108 MHz Quad SPI operation consumes 16 mA of active current. When the memory is not active, standby mode consumes 102 µA. Deep power mode drops consumption down to 0.8 µA and hibernate mode achieves the lowest consumption at 0.1 µA.
The availability of multiple power modes with different wake-up times enables developers to reduce total power consumption based on the application’s needs. When the display is being used, memory will be in active and standby modes based on when the memory is accessed for burst reads. When the display needs to be inactive for a short duration, deep-power down mode can be used. When the device will be inactive for a longer duration, hibernate mode can be used.
Figure 2. Cypress PSoC® 6 + Excelon F-RAM based display solution (Source: Cypress)
Figure 2 depicts a typical implementation using serial F-RAM. The CPU is responsible for writing the initial display data into the frame buffer. Once written, the LCD controller will initiate a periodic refresh of data from the F-RAM frame buffer to the LCD display. Designing with F-RAM achieves >30 frames per second (fps) for wearable displays. Typical fps which can be achieved in various display sizes with QSPI F-RAM are shown below.
|Resolution||Color Depth||Frames per Second (fps)||% Memory inactive time|
|320 x 240||16‑bit||25||0%|