Software-driven power analysis

July 10, 2019

jstahl-July 10, 2019

Emulators do not generate activity profiles by default; a novel power analyzer tool is required to create a weighted activity model and load it in the emulator along with the design. Adding multi-threaded power analysis engines to the emulation run produces the profiles that enable users to analyze power usage of their designs systematically when executing multi-billion-cycle, complex software workloads. Users can run this power analysis step as soon as the register-transfer-level (RTL) design is ready. Since power estimation grows more precise for each stage in the implementation flow, users can run the same analysis on the post-synthesis gate-level (GL) netlist (see Figure 2). Since total power consumption is the target metric, whenever possible the complete chip-level RTL or netlist should be used.

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Figure 2. Selection of power critical windows (Source: Synopsys)

The next step in the process is to replay (re-run) each power critical window in the emulator to generate much more detailed information on power consumption and switching activity. Since this can be a great deal of data, it is impractical to run the entire multi-billion-cycle workload. The emulator must support save and restore so that each portion of the workload identified as a power critical window can be replayed by itself quickly and easily. For the replay, emulation can start at the save/restore point closest to the window. The emulator must also be able to record stimuli during a test run so that the replay happens deterministically. These same requirements apply for efficient debug in emulation as well as for practical power analysis.

The results from the power critical window replay are fed into the power analyzer, which produces two results. The first is a switching activity interchange format (SAIF) file, which documents the switching activity of every signal in the design. As a benchmark, this flow should be able to generate a 100 million cycle SAIF file from 1 TB of emulation data in two hours. Given appropriate output from the emulator, this file can be 100% accurate. As such, it provides deep insight into design activity and enables more accurate power consumption estimation. The SAIF file generated by the power analyzer is fed into the power signoff tool (see Figure 3), which calculates the average power consumed during the window. This is very useful for users trying to understand the power requirements for the final chip.

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Figure 3. Estimation of average power (Source: Synopsys)

The power analyzer also generates cycle-by-cycle power consumption values for the entire power critical window. Users can view this information in the debug tool and use it to select one or more power signoff windows where highly accurate power estimation is needed (see Figure 4). In addition to the completeness of the SAIF file, the power analyzer has access to the detailed libraries for the target chip technology, including power characteristics. Thus, power analysis at this stage is typically 95% accurate when compared to the final chip. The user can feed the power signoff windows to the power signoff tool to refine the power analysis even further. The power signoff tool can calculate peak power for the window, allowing the user to ensure that power consumption stays within the physical limits for the chip. If IR-drop analysis is required, one or more event windows can be selected to run in the appropriate tool.

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Figure 4.Selection of power signoff windows (Source: Synopsys)

Since later refinements in the design flow enable more accurate power analysis, the user may wish to run the power analyzer and the power signoff tool on RTL, the post-synthesis netlist, and the placed-and-routed netlist. The user might also want to analyze a netlist with an engineering changed order (ECO) implemented in it to be sure that power consumption has not been affected materially. Users should be able to create both a zero-delay waveform for fast analysis using the backend tool capabilities or a more accurate delay-annotated waveform for more accurate backend analysis (see Figure 5).

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Figure 5. Power analysis calculations for multiple delay models from a single emulation run (Source: Synopsys)

Real-world results

Synopsys offers a software-driven power analysis flow that meets all the requirements previously discussed (see Figure 6). It greatly reduces the risk of missing critical power issues by enabling use of realistic software workloads rather than synthetic tests. It delivers accurate average power and cycle power results for multi-million cycle windows 1,000 times faster than simulation-based approaches. The following table shows examples from real-world customer designs:

Application Emulated


Output Format Time
Mobile SoC 10M SAIF 2.5 hours
Processor 120M SAIF 2 hours
Processor 400M SAIF 4 hours

The flow supports emulation efficiency by reusing emulation results when analyzing power for different gate-level implementations. The power analysis flow integrates with familiar debug technology, enabling users to efficiently and accurately pinpoint and fix power-related issues.

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Figure 6. Synopsys software-driven power analysis flow (Source: Synopsys)


Power consumption is now a major concern for developers of many chips and systems, from portable, battery-operated devices to the largest racks of compute servers. Power requirements appear even in the earliest product specifications, low-power design techniques are employed throughout the development process, and accurate power estimates are required at multiple points in the process. These calculations must be made using real software workloads running in emulation to predict both average and peak power. The software-driven power analysis flow outlined in this article uses the most advanced technologies and techniques for a solution much faster and far more accurate than traditional simulation-based methods. A commercial implementation of this flow is available today. To find out more about Synopsys emulation products please visit

Dr. Johannes Stahl is Senior Director, Product Marketing, Emulation, at Synopsys, where he is responsible for emulation and Verification Continuum solutions marketing. He has more than 25 years of industry experience including technical and business responsibilities for tools and services for SoC design and software development. Before Synopsys, Dr. Stahl had marketing responsibility in the executive team at CoWare, where he was managing major product lines as well as all IP partner relationships. Dr. Stahl holds Dipl.‐Ing. and Dr.‐Ing. degrees in Electrical Engineering from Aachen Technical University, Germany.

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