Software-defined silicon: Why can't hardware be more like software?
Over the years, embedded systems designers have used different approaches to design systems in ways that optimize and customize hardware to fit the specific requirements of the application they're developing. Broadly speaking, these approaches fall into three categories:
• Processors, where the behavior of the device is defined using software programming languages, and the target is a processing engine that interprets and executes the instructions. Examples include microprocessors, microcontrollers, and DSPs.
• Configurable hardware, where the behavior of the device is defined using hardware description languages, and the target is a set of general-purpose functional resources that can be functionally configured but not physically changed. Examples include FPGAs and PLDs. The functionality is set at power-up (field-binding).
• User-specified hardware, where the engineering team creates custom physical silicon to implement the target device. This ranges from a minimal effort such as a gate array to a fully-customized device with handcrafted features. The functionality is set during manufacturing (fab-binding) and is immutable.
All three of these categories are well suited for different types of designs and all have evolved over time to take advantage of the capabilities available with new semiconductor technology. What hasn't always evolved so gracefully are the design methods and tools.
Among other things, each category has evolved its own unique set of design tools and design flows. Although there have been efforts to smooth the often significant differences between them--for example the development of C-language extensions such as Handel-C and SystemC in FPGAs--these domain-specific tools and methodologies often work at cross purposes in an integrated development environment.
This trend has accelerated as more gates have become available through programmable logic, and embedding processors into ASICs and SOCs has become straightforward. Thus it appears likely that the next generation of hardware will be increasingly programmable, blending processors and configurable hardware. It is also likely that it will become a dominant factor in custom ICs, much as programmable logic became pervasive starting 20 years ago.
The next step: software defined silicon
Given this trend, it may be the time to take the next evolutionary step in hardware design and in the tools to support them: a software-defined silicon (SDS) architectural approach that does more than just smooth over the discontinuities and provides a common design flow that is largely software driven and uses familiar software development paradigms.
Although SDS may initially sound too blue-sky and unrealistic, when you analyze existing designs what emerges is that nearly all "hardware" has some software components. Ranging from simple state machines to embedded software processors, an instruction-set type of control machine lives in most custom devices. Software has made these inroads into hardware because software is substantially simpler to modify, update, and maintain--key requirements in complex systems moving forward.
The SDS approach takes this software-oriented approach to the logical next step. It is based on a multicore array processor architecture built around the concept of communicating sequential processes.
The processors used in each element of the array are general purpose in the sense that they can execute conventional sequential programs. However, when used in concert, they form a general purpose concurrent architecture with hardware resources for scheduling a collection of concurrent processes and for performing synchronization, communication, and input-output tasks.
This approach allows the description of systems in terms of component processes that operate independently and interact with each other solely through message-passing communication. It allows component processes to be defined both as sequential processes and as the parallel composition of more primitive processes.
A software-defined silicon architecture based on communicating sequential processes makes it possible to build efficient multicore chips scaling to hundreds of processors. Concurrent processing, communications, and input-output are supported directly by the instruction set of the cores and by the protocol used in the on-chip interconnect.