Applying Design for Manufacturing (DFM) to PCB development
Insufficient solder mask between two pads was a third DFM issue with
this high-speed design. Here, pads were placed extremely close
together. The result was that the solder mask was too thin, and it
peeled off during the entire process. In turn, that caused solder to
flow in a sliver from one pad to another. What had happened was that the
discrete components didn’t have a uniform pad definition due to that
lost sliver, as shown in Figure 4. Consequently, the component was being shifted from the smaller to the larger pad.
Another pad problem in this design had to do with mismatched pad sizes, this time in the power supply portion of the layout. Very fine 0402 metric (0.4 mm x 0.2 mm) passive device packages were used, which are not recommended for power layouts. In this situation a Savvy PCB layout engineer would have used 0603 thick film chip resistors with 1608 metric package sizes or maybe 0805 thick film chip resistors with slightly larger 2012 package sizes. But nothing smaller.
The reason for this caution is that most power layouts have large copper pours on external layers. In this high-speed design example with the 0402 packages, one side connecting directly to a copper blob. The other side just had a trace and a via. As a result during reflow, that copper blob acted as a heat sink producing a cold solder joint on one side of the pad. To alleviate that issue it is best to create thermal connections from the pad to the copper. Better yet, use a larger package.
Other examples of sabotaged DFM
There are other layout missteps that can sabotage efforts to apply effective DFM principles to printed circuit boards. Poorly executed PCB layout can cause fabrication and assembly problems relating to pad definition, component footprint, layer stack-up, material selection, fan out, trace width, and trace clearance. For example, poor pad definition can cause opens and shorts at assembly while an inaccurate component footprint can cause non-manufacturability if the component library isn’t correct.
At layer stack up, the designer has to make sure the right uniform stack-up is used to avoid warping. He or she also needs to know PCB material requirements to include field requirements. Meanwhile, a keen design eye has to be placed on fan out. If not performed properly, acid or etch traps occur, thus causing trace damage. Also, if not designed correctly, trace widths and clearances are other stages that can lead to shorts.
Fabrication stage problems. At this stage of the PCB design and fabrication process Warping occurs when small amounts of chemical, usually acidic, collect in what are called “acid traps” at the acute angles in a PCB trace. (Figure 5). When that chemical isn’t cleaned up, it can eat away at the traces even after assembly and/or it can cause intermittent connections while the product is in the field. Even in small amounts this can even eat away an entire trace if it is small enough and happens early at the trace width stage or later at the fan out stage of a layout.
Registration and aspect ratio issues When the PCB has many layers with fine lines and spacing they may cause mis-registration of holes and pads. Such registration problems on pads and vias during fabrication can cause multiple shorts, or even totally destroy the board.
Aspect ratio issues occur at early fabrication stages when the PCB goes into computer-aided manufacturing (CAM) and the fab shop finds out the aspect ratio isn’t correct. In this instance, hole sizes are extremely small and PCB thickness is considerable. Therefore, the fab shop either has major difficulties or isn’t able to fabricate that board.
Copper and solder mask slivers As discussed earlier, copper slivers come about because the PCB has copper features on external layers. Extremely small, one-ended copper traces – slivers - can protrude out of the PCB anywhere and any time to cause shorts after assembly.
Solder mask slivers occur when there isn’t enough solder mask between pads and vias. There are a number of causes for this phenomenon, including incorrect placement, incorrect pad definitions, and/or placing exposed vias too close to component pads.
Stepping through key layout stages
80 percent of PCB layout errors happen due to incorrect part geometry or creation, bad hole definition, inadequate spacing between through holes and surface mount components, and lack of rework ability around critical components.
As a result the PCB layout design engineer has to move gingerly through various stages to avoid such fabrication and assembly problems. For example, BGAs requiring rework may be placed too close together. As a result, rework cannot be performed. Also, vias or pads may be too close to the board’s edge, which can cause vias to be cut away during routing.
Then there are fiducials, which are marks on a PCB that provide common measurable points for each and every assembly step. They permit PCB assembly systems to precisely zero in on the circuit pattern. Fiducials are used to properly align SMT (surface mount technology) cameras, which are used during the PCB assembly pick and place phase to identify and help place components in their respective locations. Typical positional tolerance of these cameras is +/- 1 mil.
Without fiducial markings to allow the SMT cameras to align properly, tombstoning occurs because there is mis-registration between the pick-and-place camera and the board. When it comes to fine pitch components, the PCB designer needs to make sure there are extra fiducials around those components to aid the SMT camera.
As noted earlier, increased spacing is necessary for BGA efficiency. There are other issues arising from BGA use such as coefficient of thermal expansion (CTE) mismatches between the BGA and the boards due to improperly selected PCB material. If CTE is not comparable, solder joint fatigue can cause opens on the BGA. Also, symmetrical board stack-up is crucial when using BGAs. Otherwise, solder joint fatigue and board warping occur.
Using via-in-pads for BGAs is another area the PCB layout designer must be careful about. Via-in-pad is widely popular, especially for finer pitch BGAs below 0.75 mm. Compared with dog-bone fan-outs, via-in-pad increases density and allows the use of finer pitch packages. Also, decoupling capacitors can be placed directly over the vias on the opposite side of the BGA, thus reducing intrinsic inductance.
However, there are drawbacks as well as advantages to using using via-in-pad. When using via-in-pad, conductive and non-conductive material is used to fill the vias and then plated over. If the fab house isn’t knowledgeable about this process, a number of issues can occur. In particular, moisture entrapment is a risk, which wreaks havoc at assembly. When moisture is trapped, vias and pads can be popped and dimples can form during reflow that can destroy BGA pads. A popular approach to avoiding extensive expansion or contraction is to use non-conductive via fillings, which reduces moisture entrapment.
Syed Wasif Ali is an advanced certified designer (CID+) and a layout engineer at Nexlogic Technologies, Inc., San Jose, CA. He received his BSEE from N.E.D. University of Engineering and Technology in Karachi Pakistan. He has over 7 years of PCB design experience.