Applying Design for Manufacturing (DFM) to PCB development

Syed Wasif Ali, Nexlogic Technologies

March 16, 2014

Syed Wasif Ali, Nexlogic TechnologiesMarch 16, 2014

In design for manufacturing (DFM), PCB design layout engineers can easily overlook key factors that at first glance don’t appear significant. But later on, these factors play a major role during manufacturing and can turn out to be the root cause of poor yields.

When it comes to high-speed PCB designs, above 20 GHz in particular, lack of communication and/or faulty assumptions between PCB designers and the manufacturing team can lead to costly failures during manufacturing. Following are some real-world scenarios in which communication problems have occurred and some tips on how to avoid such problems.

Scenario #1: Reduce pad size to match trace width
In this case, the PCB designer had reduced the pad size to match the trace width. He didn’t think twice about it; it is quite acceptable to do so. Unfortunately, it was reduced so much that this misstep violated IPC and manufacturing rules.

The consequence was a number of issues in manufacturing and in particular, tombstoning occurred, as shown in Figure 1. Tombstoning is a component defect that occurs at the PCB assembly stage due to the solder’s surface tension during reflow. As a result, one end of the component is detached from a PCB’s copper pad and lifts up vertically, resembling a tombstone.

Figure 1: Tombstoning

This situation came about because solder was flowing into the trace because it was the same size as the pad, and there was movement during reflow. The result was a mismatched pad size. Together with other DFM issues, yields were below 60 percent, far below the expected 90 percent.

Other DFM problems included:
  • Solder shorts caused by a gang relief mask
  • Use of thermal vias caused solder wicking through the barrel
  • Insufficient solder mask between two pads

Actually, the PCB designer’s decision to make the trace width as the same size as the pad was indeed correct: in any high-speed signal, discontinuities in impedance are created when a signal’s geometry changes, which in turn changes impedance of a trace. By using the same trace width as the pad size, signal geometry would not change and the amount of discontinuity is reduced when the trace enters the leads of the discrete component pad. In theory this works. However, in practice, manufacturing issues arise when the same size is used for both traces and pads that are too small, resulting in tombstoning and other assembly issues.

Specifically, in this case, the fan out trace is the same size as a pad. Here a ball-grid array (BGA) package is used, with the BGA pads fanned out with a thicker trace. If it’s not a non-solder mask defined (NSMD) pad, the solder flows into the traces for those particular pads, causing a non-uniform pad size forming under the BGA, and subsequently forming cold solder joints or voids, as shown in Figure 2.

Figure 2: Voids in a BGA

Scenario #2: RF filter problems
In this case, the high-speed design included a specialized RF filter in a three-pin SOP package. Solder mask was not used in between the pins and it was gang relieved, which is a method of defining a solder mask so that the mask is avoided around a group of pins. The result is a set of pins that don’t have solder mask in between. This may be done intentionally or may be a mistake on the part of the PCB designer. The result was solder shorts between the three pads of the filter.

Also, in this case the vias are extremely close to the pads. In fact, half the via encompasses the pad. That only happens if the via’s pad is on top of the component, rather than on the hole. This is a no-no: the hole should never overlap the component’s pad.

In this case, the vias encroached on the component pad, which caused solder to wick through the barrel to cause tombstoning and opens. There are a couple of ways to fan out of the discrete component to avoid this situation. With an eye to design for manufacturing, the best way is to position the via slightly further away from the pad where there is solder mask between the pad and the via hole.

A second way isn’t ideal for fan out. Here the via pad encroaches on the component pad, but not the hole. The result? When the via is tented, there is less likelihood of solder wicking through the barrel. There are two ways to solve this problem. The first option is to put the via directly on top of the pad and have it filled with a non-conductive fill. The second option is to move the via slightly and place solder mask between the hole and the pad.

For this particular high-speed design, a recommended land pattern from the manufacturer was used. The problem is that those recommendations were for low volume prototyping, not for production. A land pattern is one created in the CAD layout tool so that a PCB component can be soldered and makes connections to the PCB by means of an outline of the components as well as pads that will allow pins to be soldered to them.

But when a large number of parts is used on extremely dense boards, it is critically important that the land pattern be modified based on the assembly house’s recommendation.

Then there is the issue of the hole size. It has to be 0.3mm or less, so that the via closes very early in reflow. Ideally, it’s best to have the via shut and plated, but that never happens. For thermal vias, 0.3mm pitch or even finer is all that is necessary to prevent solder from wicking through the barrel.

In our high-speed design example, vias the OEM used measured about 15 mils, but ideally they should be less than 8 mils. Because they were not the correct size, during manufacturing solder was flowing down the barrel due to the larger vias. This caused a suction action on a separate SOP package in the board design that shorted out the peripheral pads (Figure 3).

Figure 3: Solder going down the barrel due to the larger vias, causing suction action on a SOP package and resulting in shorts on the peripheral pads.

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