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Bringing experimental development methods to PCB design and manufacturing

Zulki Khan, NexLogic Technologies, Inc.

December 03, 2014

Zulki Khan, NexLogic Technologies, Inc.December 03, 2014

PCB technologies are undergoing a major new evolution unlike anything the industry has seen before. Issues relating to PCB size, shape, complexity, thermal requirements, and shrinking board space are creating design and assembly/manufacturing challenges for the original equipment manufacturers (OEMs), chip and component makers, material suppliers, and the electronic manufacturing services (EMS) providers. The effort to resolve these issues is changing the dynamics among these key players.

These challenges are pushing PCB design and manufacturing methods to newer levels and are creating demands for more efficient device packaging, newer substrate alloys, and better soldering pastes and fluxes to meet new printed circuit board (PCB) assembly and manufacturing requirements. But the major OEM requirement is for a research and development-like environment within which to conduct experiments to prove or disprove the validity of the new techniques in next-generation embedded systems.

Design of experiments (DOEs)
Consequently, EMS Providers are being called upon to take on the task of ‘design of experiments’ or DOEs, also known as experimental designs, requiring them to work with OEMS to do the necessary research and development. A DOE is an information gathering exercise where variation is the main characteristic. It can be performed as a fully controlled set of experiments, or as a partially controlled set of experiments that involve changing one variable and keeping everything else the same.

For example, it could be the chemical formulation of a flux that’s made differently or it could be different composition of materials. In a specific case, the component of metal balls of the solder powder is different. At times, the acidic level of sulfate in the fluxes is different. This would make it a quasi-experimental design or fully natural experiment in which some of the elements in the design are changed, but others are not.

The objective is to collect as much information as possible by doing the same experiment in a variety of ways to achieve the OEM’s objective. Experimental designs can be used at the point of greatest leverage to reduce manufacturing complexity and introduce new technology. When the prototype is being designed and manufactured, there is some uncertainty about how the design will work and any way to speed up up the process can reduce the time it takes to verify the functionality of the product as well as final time to market. It also reduces the design chain cycle time, product material requirements, and labor complexity. When these changes are made, an advanced type of flux may be used. Simultaneously, the associated thermal profile needs to be adjusted.

Forces driving DOEs
A key driving force for DOEs is the fact that shrinking board space is placing heavy demands on chipmakers to manufacture their devices in smaller, yet efficient packaging. Previously, EMS providers dealt with devices and components in larger packages and device packages with gull-wing leads sticking outside the actual package and onto the board, thus making it easy to assemble and inspect them. There was ample PCB real estate for earlier generation packaging.

But now, leadless packages are used to conserve board space and provide both better performance and improved heat transfer. Also, since board real estate is tapped out, components are stacked on top of each other for a package-on-package (PoP) design arrangement, as shown in Figure 1. However, when packaging becomes so small, PCB design and layout become highly challenging.


Figure 1: When PCB real estate is at a premium, components are stacked on top of each other for a package-on-package (PoP) design arrangement. (Photo courtesy of MyData Corporation)

Further, as shown in Figure 2, thieving (or ground pour), the traditional copper overlay on boards to help dissipate heat, cannot be used in most cases with those shrinking PCBs. There’s simply no space left to perform ground pouring.


Figure 2: Thieving or ground pour, the traditional copper overlay on PCBs to help dissipate heat, cannot be used in most cases with shrinking PCBs.

These are only a few samples of the many issues and challenges OEMs face as they move into newer system frontiers. DOEs help resolve them with their varying experiments and successful results.

Pushing the technology envelope
Types of DOEs include, but are not limited to, the following:
  • Crystalizing futuristic technologies
  • Checking out newer solder pastes and fluxes to comply with ever-changing tight ball-grid array (BGA) pitch
  • Resolving anticipated technology issues in subsequent product generations
  • Determining long-term product reliability
  • Evaluating different PCB design and assembly practices to improve product yield

Most often, the common denominator among DOEs is the fact that the OEM is intent on pushing the technology envelope. Working off their imagination, designers know they can design practically any new and innovative product using state-of-the-art electronic devices. However, they also are well aware that there can be manufacturing limitations.

Those limitations involve different processes, physics laws, and different mechanical, electrical, and manufacturing constraints. Still, venturesome OEMs want to explore those frontiers.

Take for example the OEM who figured his LED application would fit nicely in conventional chip on board (CoB) packaging. However, prior to assembly, he learned differently. There were three major issues: board warpage, thermal management, and little to no pad adhesion of the CoB to the PCB’s surface.

The LED/CoB was large, measuring about an inch long. The PCB that the CoB was assembled on was 40 mils thick rather than the regular thicker one of 62 mils. In this case, there was warpage on both the CoB and the PCB itself, even when undergoing a single reflow cycle. The CoB was warping due to its size; the PCB was warping due to its minimal thickness.

Plus, a significant amount of thermal energy the LED generated could not be transferred from the CoB to the PCB and then to the ambient; the heat generated by the CoB was trapped underneath the package. The lack of pad adhesion was due to the tiny 25-mil pitch pads. During printing, as a result of the small size of the pads the adequate amount of solder paste wasn’t being dispensed. Hence, there was no good adhesion although the PCB had an electro-less nickel immersion gold or ENIG surface finish.

The solution was hybrid proprietary BGA (ball-grid-array)-like packaging. In this arrangement:
  • The package has BGA balls situated at the four corners, allowing efficient adhesion.
  • The balls also provide the necessary thermal escape routes to the ambient.
  • BGA-like adhesion to the PCB was properly performed since pads were eliminated and replaced by the BGA balls.
  • Thermal management became considerably more efficient since now there is sufficient BGA ball diameter. That greater area on each BGA ball removes the thermal energy more effectively, and it goes to the PCB’s surface for heat dissipation.
  • Warping is eliminated because the package is more robust.
  • It allows the LEDs to shine from the package’s underside and through a hole created in the PCB.

Another example of DOE is when a very tight BGA pitch is involved. In this instance, another OEM came up with a highly advanced design populated with a number of 0.25 mm pitch BGA devices. Earlier, BGA ball pitch was one millimeter. Subsequently, it got smaller, going to 0.8 mm, 0.5 mm, and finally 0.3 mm. At those geometries, two 5 or 4 mil traces can be run between two adjacent BGA balls. Circuitry can then be cleanly connected without jeopardizing the current load going between those two traces.


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