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Building 491MHz FPGA-based wireless radio heads

October 13, 2015

Michael Parker-October 13, 2015

Editor's Note: In this series of design articles, the authors offer a close look at various design challenges and effective use of design tools and techniques for resolution of those challenges. Be sure to check out the first article in this series: Model-based FPGA design tool quietly gains adherents

Today’s 3G and 4G wireless systems require an enormous amount of signal processing. The smart phones offer ever more features and capabilities, but behind all of this connectivity is the wireless infrastructure. FPGAs play a key role in the hundreds of thousands of wireless base stations supporting our communications network. Smart phones demand much greater data bandwidth, which puts more pressure on the network, demanding greater performance from the FPGAs within.

Due to particulars of the 3G UMTS and CDMA wireless standards, the signal processing circuits operate at multiples of 61.44 MHz. The 3G base stations typically operated at 245.76 or 368.64 MHz. The newer 4G base station designs are targeting 491.52 MHz, which is extremely challenging to support across large designs in the latest FPGAs.

These designs can be built using HDL (Verilog or VHDL) by expert FPGA designers. Alternatively, there is one high level toolflow capable of delivering the required performance: DSP Builder Advanced Blockset. This article will describe in detail the design, performance and resources of radio head design built using DSP Builder on Altera’s 20nm Arria 10 FPGAs.

Base station architecture
The base station architecture is generally divided into two sections. The baseband section performs the OFDMA/CDMA modulation and demodulation, error correction and generally all the L1 functions in the standard, and is often located at a central office location. The radio section implements the functions closely associated with the antennas: digital up and down conversion, crest factor reduction, and digital pre-distortion. Often referred to as the remote radio head, it is typically located on the antenna tower or in cabinets at the base of the antenna tower.

An antenna site typically supports three sectors, each nominally covering 120 degrees. Each sector radio head can be further described by the number of transmit antennas, the number of receive antennas, and the number of RF carriers (sometime called channels) supported per antenna.

The interface to each antenna is through serial JEDS204B interfaces to the receive ADC and transmit DAC, each operating at 491 MSPS. The interface to the baseband processing is through the CPRI protocol, supporting serial interfaces to the baseband processing. A system with two receive and two transmit antennas is shown in Figure 1.                    


Figure 1: Wireless Radio Head Block Diagram

Functionally, the processing blocks are show below in Figure 2. In this case, each antenna supports two RF carriers. While the data rates vary for each block, the clocking rate for each block is 491 MHz. Up to 8 RX and TX antennas can be supported in a single FPGA.


Figure 2: Radio Head Signal Processing Chain

Digital upconversion begins with FIR filters. At the lower sample rate of consists 30.72 MSPS, the channel shaping filtering is performed. This will limit the spectral width. To increase the sample rate, for example to 122.88 MSPS, half-band filters are used. The DSP Builder toolflow produces optimal structures for both type of filters, taking advantage of all the special hardware features of the chosen FPGA. The hardened DSP blocks include built in fixed coefficient register banks, pre-adders for symmetric filters, systolic post adder structure, and biased rounding, which allows for minimal use of programmable logic in FIR filter chains.

Complex Mixer and NCO circuits are also needed to modulate the signal onto the selected IF carrier frequency. This again is easily supported in the toolflow. Multi-channels are supported, without the necessity of the designer to provide control or synchronization circuits, in this case providing for 16 separate baseband channels. Best of all, the tool is able to close timing with Fmax well in excess of 491 MHz in -1 speed grade of Arria 10 FPGA.

Digital down conversion, performed in the receive path, is similar. Figure 3 depicts a design and test bench using both DUC and DDC circuits to verify proper operation in the MathWorks Simulink environment. With a sample rate of 122.88 MHz (complex), this allow for an aggregate RF bandwidth of up to 80 MHz. Individual channels are normally 5 MHz, 10MHz, or 20 MHz bandwidth, depending upon the number of OFDMA carriers in each channel.


Figure 3: Digital Up and Down Conversion

FIR filters can be designed in MATLAB, and even the FIR filter command line can be entered into the DSP Builder parameterization filed. The coefficients can be fixed, or read/writable. Alternately, a coefficient file can be provided. The filter can be folded (using data rate lower than clock rate), super-sampled (using data rate higher than clock rate), and provide rate changes (decimation or interpolation) by integer or non-integer rates. Saturation and rounding options are supported, to manage the fixed point dynamic range. Floating point FIRs are also supported, if desired.

Crest Factor Reduction
Crest factor reduction (CFR) is a more complex function, used to reduce the peak to average of the wireless signal, while minimizing impact on signal quality measured using Error Vector Magnitude (EVM) of the demodulated signal. The larger the EVM, the more distorted the demodulated OFDMA constellation will be, which in turn degrades data recovery and system performance.


Figure 4: QAM Constellation after OFDMA Demodulation

CFR allow the high powered RF amplifiers to operate more efficiently, which allows for higher RF transmit power and reduced power dissipation in the radio head.

Two CFR methods have been explored using DSP Builder. The first method is known as “Pulse Allocation CFR”. Pulse Allocation CFR searches for the maximum peak in the signal which exceeds a defined threshold. When found, a sync pulse is generated with the correct phase and amplitude to cancel the peak energy above the threshold. The filter is also used to assure that spectral limits are not exceeded. Multiple iterations are used; the first iteration will cancel the largest peaks, leaving remaining nearby peaks to be cancelled by subsequent peaks. The input data is processed in blocks.


Figure 5: Pulse Allocation CFR Block Diagram

All of this can be readily implemented in DSP Builder, which allows the designer to focus on algorithm verification, and let the tool deal with optimizing the design to the FPGA architecture, and pipelining as necessary to meet the aggressive Fmax requirements.

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