Selecting the right hardware configuration for the signal processing platform

November 21, 2016

VisualSim-November 21, 2016

The quality of signal processing systems such as a software defined radio or a communication modem is dependent on the performance of the selected hardware platform. Early design explorations enable the designer to gain insights into implementation challenges, architectural decisions to enhance performance and power, and hardware/software partitioning before Register-Transfer level (RTL) and software are available.

In addition, early design explorations assist architectural design decisions that facilitate planning for current and future requirements. Designers can further extend the design explorations to conduct fault analysis and identify test cases for verification.

This article presents the system level modelling and simulation methodology to architect a signal processing platform for software-defined radios or high-speed communication modems early in the design flow.

The majority of complex systems such as advanced high speed signal processing platforms go through expensive design iterations. Over 70% of the time iterations are due to incorrect design decisions or misunderstanding about the requirements. In addition, numerous factors influence such complex systems. A few of them are low processing latency, low power, configurability and limitations in resources. Early design explorations help overcome such issues.

Designers and architects follow number of ways to conduct design explorations and analysis. Though analytical methods provide significant information on the worst-case execution time, majority of the range do not occur in real life. Physical testing methods may provide accurate information, but are not feasible for complex systems such as SDRs or High Speed Communication modems.

Discrete event simulation enables designers and architects to evaluate a target system with hundreds or thousands of use cases, task scheduling, and system configurations in a shorter time frame. Discrete Event Modelling and Simulation helps not only in constructing extremely complex simulation models but also enables architects and designers to run extensive set of use cases and probabilities.

In addition, availability of pre-built and validated libraries of hardware architectural components and framework assist in modelling software architecture. They improve the accuracy of the system model and reduce the time to construct simulation models.

This approach allows designer to

  • Focus on analysis and interpretation of results rather than constructing models.

  • Optimize product architectures by running simulations with application profiles to explore platform selection; hardware versus software decisions; peripheral devices versus performance; and distribution of software threads on target architectures.

Solution Implementation
This article presents the design exploration of a signal processing platform. The purpose of the design explorations is to capture processing latency, Field-Programmable Gate Array (FPGA) Buffer Requirements, impact of packet length on performance, and identification of hardware platform configurations. The explorations can be further extended to understand resource utilizations for each signal processing functions such as peak finding, correlator, weighted multiplications, and accumulator.

The discrete event simulation model utilizes the following components:

  • Four ADC Channels at 5 MHz.

  • Packet Length of 512 and 1024 Bytes.

  • FIFO at 233 MHz.

  • Buffer with a Depth of 1024.

  • FPGA Initial Clock Speed is 125MHz. FPGA Clock Speed can be varied to meet latency requirements.

  • External DDR Memory running at 167 MHz.

  • ADSP TS201 running at 260MHz.

Models are constructed graphically using VisualSim Architect’s pre-built configurable libraries. Processors, memory, FPGA Resources, Buses and Interconnects are modelled using VisualSim “SystemResource” library blocks. Analog-to-digital Converters (ADCs) are modelled as traffic generators and are responsible for generating digital samples at 5MHz.

In this system exploration, we considered abstract details for each function. The details can be leveraged to create an elaborate model by integrating matlab/simulink/C/C++ modules. For each function, we have considered timing values from existing Verilog code running in system generator and standard published values. Sum of weighted inputs are forwarded to Digital Signal Processor for display processing and floating point FFT and then the data is written into Frame Buffer for display.

Block diagram of the proposed system platform is shown in figure 1 and the VisualSim simulation model is shown in figure 2.

Figure 1. System Block Diagram (Source: Courtesy Mirabilis Design project report)

Figure 2. VisualSim Model of Signal Processing Platform (Source: Courtesy Mirabilis Design project report)

Analysis and Reports
The model was constructed in two person hours and the simulation was run on a 2.6 GHz Microsoft Windows 10 platform with 4 GB RAM, simulating 900.0 msec of real time. VisualSim took 25 seconds of wall clock time to finish a simulation.

Explorations are focused on achieving algorithm processing deadline time based on the packet size and capture power versus performance trade-off.

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