Flash 101: NAND Flash vs NOR Flash
Embedded system designers must take into account many considerations when selecting a Flash memory: which type of Flash architecture to use, whether to select a serial interface or a parallel interface, does it need error correction code (ECC), and so on. If the processor or controller supports only one type of interface, this limits the options so the memory may be easy to select. However, this is often not the case. For example, some FPGAs support serial NOR Flash, parallel NOR Flash, and NAND Flash memory to store configuration data. This same memory can be used to store user data, which makes selecting the right memory to use more difficult. In this article series, the different aspects of Flash memories will be discussed, beginning with the differences between NOR Flash and NAND Flash.
Flash memories store information in memory cells made from floating gate transistors. The names of the technologies explain the way the memory cells are organized. In NOR Flash, one end of each memory cell is connected to the source line and the other end directly to a bit line resembling a NOR Gate. In NAND Flash, several memory cells (typically eight cells) are connected in series similar to a NAND gate (see Figure 1).
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Figure 1: NOR Flash (left) has an architecture resembling a NOR gate. Similarly, NAND Flash (right) resembles a NAND gate. (Source: Cypress)
The NOR Flash architecture provides enough address lines to map the entire memory range. This gives the advantage of random access and short read times, which makes it ideal for code execution. Another advantage is 100% known good bits for the life of the part. Disadvantages include larger cell size resulting in a higher cost per bit and slower write and erase speeds. For more details on how NOR Flash can be used in embedded systems, see An Overview of Parallel NOR Flash Memory.
NAND Flash, in contrast, has a much smaller cell size and much higher write and erase speeds compared to NOR Flash. Disadvantages include the slower read speed and an I/O mapped type or indirect interface, which is more complicated and does not allow random access. It is important to note that code execution from NAND Flash is achieved by shadowing the contents to a RAM, which is different than code execution directly from NOR Flash. Another major disadvantage is the presence of bad blocks. NAND Flash typically have 98% good bits when shipped with additional bit failure over the life of the part, thus requiring the need for error correcting code (ECC) functionality within the device.
NAND Flash memories are available in much higher densities compared to NOR Flash owing primarily to its lower cost per bit. NAND Flash memories typically comes in capacities of 1Gb to 16Gb. NOR Flash memories range in density from 64Mb to 2Gb. Because of its higher density, NAND Flash is used mainly for data storage applications.
Erase, Read & Write
In both NOR and NAND Flash, the memory is organized into erase blocks. This architecture helps maintain lower cost while maintaining performance. For example, a smaller block size enables faster erase cycles. The downside of smaller blocks, however, is an increase in die area and memory cost. Because of its lower cost per bit, NAND Flash can more cost-effectively support smaller erase blocks compared to NOR Flash. The typical block size available today ranges from 8KB to 32KB for NAND Flash and 64KB to 256KB for NOR Flash.
Erase operations in NAND Flash are straightforward while in NOR Flash, each byte needs to be written with ‘0’ before it can be erased. This makes the erase operation for NOR Flash much slower than for NAND Flash. For example, the S34ML04G2 Cypress NAND Flash requires 3.5ms to erase a 128KB block while the S70GL02GT Cypress NOR Flash requires ~520ms to erase a similar 128KB sector. This is a difference of nearly 150 times.
As mentioned earlier, NOR Flash memory has enough address and data lines to map the entire memory region, similar to how SRAM operates. For example, a 2-Gbit (256MB) NOR Flash with a 16-bit data bus will have 27 address lines, enabling random read access to any memory location. In NAND Flash, memory is accessed using a multiplexed address and data bus. Typical NAND Flash memories use an 8-bit or 16-bit multiplexed address/data bus with additional signals such as Chip Enable, Write Enable, Read Enable, Address Latch Enable, Command Latch Enable, and Ready/Busy. The NAND Flash needs to provide a command (read, write or erase), followed by the address and the data. These additional operations makes the random read for NAND Flash much slower. For example, the S34ML04G2 NAND Flash requires 30µS compared to 120ns for S70GL02GT NOR Flash. Thus the NAND is 250 times slower.