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Flash 101: The NOR Flash electrical interface

August 08, 2018

avinashmanu-August 08, 2018

In the first article in this series, we discussed the major differences between NAND and NOR Flash. In part 2, we will focus on the electrical interface of different types of NOR Flash devices and how this impacts device selection and design. When they were first available, NOR Flash memories had a parallel interface with a parallel address and data bus. The higher signal count of parallel interfaces as densities grew made PCB design more difficult and led to the development of a serial interface that brought with it some compromise on performance. The growing demand for performance and the need for a simple interface led to the development of low signal count, high performance NOR Flash interfaces. The different interfaces are discussed in detail in the following sections.

Parallel NOR Flash Interface

As the name indicates, parallel NOR Flash is interfaced to a memory controller using a parallel address and data bus similar to SRAM. Parallel NOR Flash devices available in the market generally support an 8-bit or 16-bit data bus. The width of the address bus depends on the Flash capacity. The address bus width can be calculated as:

log2(Total capacity in bits / data bus width in bits)

For example, a 2-Gbit (256MB) NOR Flash with a 16-bit data bus will have 27 address lines.

Apart from the data and address bus, there are additional signals (see Figure 1) such as Chip Enable (CE#), Output Enable (OE#), Write Enable (WE#), Ready/Busy (RY/BY#), Reset, and Write Protect(WP#). For devices that support both 8-bit and 16-bit data bus widths, there will be an additional signal to select the bus width, often denoted as BYTE#. A brief description of the signals is given in Table 1.

Table 1: The additional signals on a parallel NOR interface, not including address or data bus lines.

Signal

Function

CE#

Input Signal, logic low selects the device for data transfer with the host memory controller.

OE#

Input Signal, controls whether outputs signals are actively driven or in high impedance

WE#

Input Signal, controls the direction of data transfer between host and device.

RY/BY#

Output Signal, indicates whether the device is executing any operation or ready for next operation.

RESET#

Input Signal, hardware reset, causes the device to reset control logic to its standby state.

WP#

Input Signal, disables program and erase functions for the protected sector of the device.

BYTE#

Input Signal, indicates the data bus width for devices with 8-bit & 16-bit data bus support


Figure 1: The signals used in a parallel NOR interface. (Source: Cypress)

The major advantage of the parallel interface is random access. The main disadvantage is that the higher signal count increases device size, requires more PCB area, and makes PCB routing more difficult.

Serial NOR Flash Interface

Serial Flash was developed to overcome the disadvantage of higher signal count in parallel Flash memory. The serial interface has significantly fewer signals, allowing a smaller device package and easier PCB routing. The downside is that one of the major advantage of NOR Flash, direct random memory access, has been sacrificed.

Serial NOR Flash typically uses the Serial Peripheral Interface (SPI) protocol to interface with the memory controller. To achieve higher throughput, dual SPI and quad SPI interfaces are available. Another feature used in serial NOR Flash to further enhance throughput is Double Data Rate (DDR) signaling. DDR transfers data on both rising and falling edges of the clock signal.

The serial Flash interface consists of the following signals (see Figure 1): Chip Select (CS#), Serial Clock (SCK), Serial Input (SI), Serial Output (SO), Write Protect (WP#), HOLD# and optional Reset input. The SI and SO signals are used as bidirectional data transfer lines for dual and quad interfaces. WP# and HOLD signals are used in quad interfaces. A brief description of the signals, considering a quad SPI interface, is given in Table 2.

Table 2: The signals used in a serial NOR interface.

Signal

Function

CS#

Input Signal, logic low selects the device for data transfer with the host memory controller.

SCK

Input Signal, reference clock for data/command transfer

SI / IO0

Serial input for single bit interface, bidirectional IO0 for dual and quad interface

SO/ IO1

Serial output for single bit interface, bidirectional IO1 for dual and quad interface

WP#/ IO2

Write Protect input for single bit interface, bidirectional IO2 for quad interface

HOLD#/ IO3

Hold input for single bit interface, bidirectional IO3 for quad interface

RESET

Optional Input Signal, hardware reset, causes the device to reset control logic to its standby state.


Figure 2: The signals used in a serial NOR interface. (Source: Cypress)

The majority of the serial Flash available in the market are footprint compatible between manufacturers, making it easier to change devices even after the design phase is completed. This enables developers to not just change between manufacturers but also migrate to the latest NOR Flash devices available without having to completely redesign the system.

Low Signal Count, High Performance NOR Flash Interface

Combining the advantages of both parallel and serial interfaces is the HyperBus interface. Using 11 signals, HyperBus supports throughputs up to 400MB/s. The Xccela Bus is hybrid bus for NOR Flash which uses a similar 11-signal interface and achieves similar throughput to HyperBus.

The HyperBus interface consists of an 8-bit bidirectional data bus (DQ), read-write data strobe (RWDS), clock input (CK), and chip select (CS#) input. There are also a few optional signals, including reset input (RESET#) to the slave (memory) device, reset output (RSTO#) from the slave device and interrupt output (INT#) from the slave device. A brief description of the signals, considering a slave device, is given in Table 3.

Table 3: The signals used in a hybrid HyperBus interface.

Signal

Function

CS#

Input Signal, logic low selects the device for data transfer with the host memory controller.

CK

Input Signal, reference clock for data/command transfer

DQ [7:0]

Bidirectional, 8-bit data bus

RWDS

Bidirectional signal, Read-Write Data Strobe. Input for command/address and read transactions, output for write transactions.

RESET#

Optional Input signal, hardware reset, causes the device to reset control logic to its standby state.

RSTO#

Optional output signal, to indicate Power-on-Reset occurring in slave device

INT#

Optional output signal, interrupt output to master from the slave device


Figure 2: The signals used in a hybrid HyperBus interface. (Source: Cypress)

The clock rate in HyperBus can go up to 200MHz. Combined with DDR signaling and an 8-bit data bus, this means HyperBus can achieve throughputs up to 400MBps. The details of HyperBus interface is available in the HyperBus Specification. The Xccela interface also uses an 8-bit data bus with DDR signaling to achieve 400MBps throughput. The specifics of how the Xccela protocol differs from HyperBus are not yet available to the public.

Developers have several options of NOR Flash interface to choose from. Parallel NOR Flash devices make an excellent choice for applications requiring random read access. Serial NOR Flash is suitable for applications requiring a simple interface and the advantages of NOR Flash except for random access. The HyperBus and Xccela interfaces combine the advantages of both serial and parallel NOR Flash interfaces. Depending upon the application, there are NOR Flash memories available that support all three types of interfaces, enabling developers to choose the optimal interface for their system.

In the next article in this series, we will focus on the electrical interface of different types of NAND Flash devices and how this impacts device selection and design.


Avinash Aravindan is a Staff Systems Engineer at Cypress Semiconductor. His responsibilities include defining technical requirements and designing PSoC based development kits, system design, technical review for system designs and technical writing. He has 8+ years of industry experience. He earned his Master’s Degree on Master of Science in Research on Information and Communication Technologies (MERIT) from Universitat Politècnica de Catalunya, Barcelona, Spain and B.Tech from Cochin University of Science and Technology, Cochin, India. His interests include embedded systems, high-speed system design, mixed signal system design and statistical signal processing.

 

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