Advertisement

Flash 101: The NAND Flash electrical interface

August 22, 2018

avinashmanu-August 22, 2018

In the part 1 of this series, we discussed the major differences between NAND and NOR Flash. In part 2, we focused on the electrical interface of different types of NOR Flash devices and how this impacts device selection and design. In this article, we focus on the electrical interface of different types of NAND Flash devices and how this impacts device selection and design.

The different types and generations of NAND Flash devices use a multiplexed address and data bus. The initial (legacy) NAND Flash devices were asynchronous devices. NAND Flash devices available today come in either of the two types of interfaces: a toggle NAND interface for devices manufacturer by Samsung and Toshiba and an Open NAND Flash Interface (ONFI) for devices by all other major Flash manufacturers including Cypress. The different types of NAND Flash interfaces are discussed in the following sections.

Legacy SDR NAND Interface

Traditional NAND Flash devices were asynchronous devices with a 15-pin interface consisting of an 8-bit data bus and control signals. Data transactions were governed by control signals instead of a continuous clock signal. These legacy devices used Single Data Rate (SDR) signaling, where data transactions were processed only on one edge of the control signal (RE# or WE#). The maximum throughput achievable was approximately 40 MBps.

The legacy SDR NAND Flash interface consisted of an 8-bit bidirectional data bus (DQ), chip enable (CE#) input, Address Latch Enable (ALE) input, Command Latch Enable (CLE) input, Read Enable (RE#) input, Write Enable (WE#) input, Write Protect (WP#) input and Ready/Busy (R/B#) output. A brief description of the signals is given in Table 1 with a schematic layout in Figure 1.

Table 1: The various signals in the legacy SDR NAND Flash interface. (Source: Cypress)

Signal Function
DQ [7:0] Bidirectional, 8-bit data bus
CE# Input Signal, logic low selects the device for data transfer with the host memory controller.
ALE Input Signal, one of the control signal used by host controller to indicate the type of bus cycle (command, address or data)
CLE Input Signal, one of the control signal used by host controller to indicate the type of bus cycle (command, address or data)
RE# Input Signal, control signal for read data transfer. Data is transferred at the rising edge of RE#
WE# Input Signal, control signal for write data transfer. Data, command and address are latched at the rising edge of WE#
WP# Input Signal, disables Flash array program and erase operations
RY/BY# Output Signal, indicates whether the device is executing any operation or ready for next operation.


Figure 1: The legacy SDR NAND Flash interface in schematic form. (Source: Cypress)

 

ONFI NAND v1.0 Interface

The first NOR Flash devices introduced to the market were not compatible between manufacturers, making it difficult to switch between devices from different manufacturers. To overcome a similar limitation in NAND Flash devices, the major Flash manufacturers (except for Samsung and Toshiba) established a working group known as Open NAND Flash Interface.

The initial version of ONFI specification was aimed at standardizing the pin assignments and commands for NAND Flash. The electrical interface of ONFI NAND v1.0 is similar to the legacy NAND interface with options to support some forthcoming technologies of the time. ONFI v1.0 added an option to support a 16-bit data bus or an additional independent 8-bit data bus and control signals to support up to 4 die in one package. To interface with controllers working with different logic voltage, an optional voltage rail (VDDQ) was also added as an input supply for the I/O interface. The maximum throughput achievable was approximately 50 MBps, providing ~20% improvement over legacy NAND Flash. A brief description of the signals is given in Table 2 with a schematic layout in Figure 2.

Table 2: The various signals in the ONFI NAND Flash v1.0 interface. (Source: Cypress)

Signal Function
IO [7:0] Bidirectional, 8-bit data bus (Mandatory)
IO [15:8] Bidirectional, upper 8-bit data bus for devices supporting 16-bit bus (Optional)
IO2 [7:0] Bidirectional, second 8-bit data bus for devices supporting two independent data buses (Optional)
CEx# Input Signal, logic low selects the device for data transfer with the host memory controller. (one signal mandatory, option for up to 4)
ALEx Input Signal, one of the control signal used by host controller to indicate the type of bus cycle (command, address or data) (one signal mandatory, option for up to 2)
CLEx Input Signal, one of the control signal used by host controller to indicate the type of bus cycle (command, address or data) (one signal mandatory, option for up to 2)
REx# Input Signal, control signal for read data transfer. Data is transferred at the rising edge of RE# (one signal mandatory, option for up to 2)
WEx# Input Signal, control signal for write data transfer. Data, command and address are latched at the rising edge of WE# (one signal mandatory, option for up to 2)
WPx# Input Signal, disables Flash array program and erase operations (one signal mandatory, option for up to 2)
R/Bx# Output Signal, indicates whether the device is executing any operation or ready for next operation. (one signal mandatory, option for up to 4)


Figure 2: The ONFI NAND Flash v1.0 interface in schematic form. (Source: Cypress)

 

Toggle NAND 1.0 (Asynchronous DDR NAND Interface)

To keep up with the growing demand for performance and throughput, Samsung and Toshiba introduced the Toggle 1.0 interface. Compared to the legacy Flash interface, a bidirectional data strobe signal (DQS) is added with DDR signaling (i.e., data transactions are processed on both rising and falling edges of the DQS signal). The DQS signal is driven by the host for write operations to the Flash and driven by the NAND while reading from the Flash. The Toggle DDR NAND interface can achieve throughputs up to 133MBps. Because the interface is asynchronous (i.e., it has no clock signal), the Toggle DDR interfaces uses less power compared to the synchronous interface and simplifies system design.

ONFI NAND v2.x Interface

The major difference in the second-generation ONFI standards is the shift towards a synchronous interface and DDR signaling to achieve higher throughput. The interface in ONFI v2.x is known as NV-DDR. Support for the asynchronous interface was retained for backward compatibility, but the changes were aimed at supporting synchronous interface. The majority of the interface signals remain the same as the v1.0 interface except for some small changes. The I/O bus is renamed the DQ bus, the data strobe signal (DQS) is added, WE# becomes clock signal (CLK) and the RE# signal becomes write/read direction signal (W/R#). Data is transferred on both rising and falling edges of DQS signal to achieve double data rate.

Continue reading on page two >>

 

< Previous
Page 1 of 2
Next >

Loading comments...