Flash 101: Types of NAND Flash
In part 1 of this series, we discussed the major differences between NAND and NOR Flash. In part 2, we focused on the electrical interface of different types of NOR Flash devices and how this impacts device selection and design. Part 3 covered the electrical interface of different types of NAND Flash devices and how this impacts device selection and design. Now we will focus on the different types of NAND Flash based on their internal architecture or the way data is stored in the memory cells.
Since the cost of Flash depends on its die area, Flash would be more cost effective if more data can be stored in the same area. There are three main types of NAND Flash: Single Level Cell (SLC), Multi Level Cell (MLC) and Triple Level Cell (TLC). As the name suggests, a TLC Flash stores more data in an equivalent area than an MLC, which in turn stores more data than SLC. Another type of NAND Flash is known as 3D NAND or V-NAND (Vertical-NAND). This type of Flash achieves a greater density by stacking multiple layers of memory cells vertically on the same wafer.
Floating Gate Transistor
In the first part of this series, I mentioned that Flash memories store information in memory cells made of floating gate transistors. To better understand the different types of NAND Flash memories, let’s look at the structure, workings, and limitations of floating gate transistors.
A floating gate transistor or floating gate MOSFET (FGMOS) is quite similar to a regular MOSFET except it has an additional electrically insulated floating gate between the gate and the channel.
Figure 1: A floating gate transistor or floating gate MOSFET (FGMOS) is similar to a regular MOSFET except it has an additional electrically insulated floating gate between the gate and the channel.
Since the floating gate is electrically isolated, any electron reaching the gate will get trapped there even after the voltage is removed. This provides the non-volatile property of the memory. Unlike a regular MOSFET, which has a fixed threshold voltage, the threshold voltage of an FGMOS will depend on the amount of charge stored in the floating gate. The more charge, the higher the threshold voltage. Similar to a regular MOSFET, when the voltage applied to the control gate is more than the threshold voltage, the FGMOS will start conducting. The information stored in the FGMOS is thus identified by measuring its threshold voltage and comparing it against a fixed voltage level. This is termed as a read operation in Flash memory.
Electrons can be placed in the floating gate using two methods: Fowler-Nordheim tunneling or hot-carrier injection. For Fowler-Nordheim tunneling, a strong electric field is applied between the negatively charged source and the positively charged control gate. This causes electrons from the source to tunnel through the thin oxide layer and reach the floating gate. The voltage required for tunneling depends on the thickness of the tunnel oxide layer. With hot-carrier injection, a high current is passed through the channel, giving sufficient energy to the electrons to tunnel through the oxide layer and reach the floating gate.
The electrons can be removed from the floating gate using Fowler-Nordheim tunneling by applying a strong negative voltage on the control gate and strong positive voltage on the source and drain terminals. This will cause the trapped electrons to tunnel back to the channel though the thin oxide layer. In Flash memory, placing the electrons in the floating gate is considered a program/write operation, and removing the electrons is considered an erase operation.
The tunneling process has a major disadvantage: It gradually damages the oxide layer. This is termed as wear in Flash memory. Every time the cell is programmed or erased, a few electrons get stuck in the oxide layer, thereby wearing out the oxide layer. Once the oxide layer reaches the point where it can no longer be reliability distinguished between a programmed and erased state, the cell is considered as bad or worn out. As read operations do not require tunneling, they do not wear the cell out. This is why the life of Flash memories is expressed as the number of program/erase (P/E) cycles it can support. Understanding Typical and Maximum Program/Erase Performance provides an explanation on how the typical and maximum values for program and erase performance are derived.
Single Level Cell (SLC) NAND Flash
In SLC Flash, each memory cell stores only one bit of information: either logic 0 or logic 1. The threshold voltage of the cell is compared against a single voltage level and the bit is considered as logic 0 if the voltage is above the level and as logic 1 if below.
Figure 2: The voltage in an SLC Flash cell is compared against a threshold voltage to determine if it is a logic 0 (above the threshold) or logic 1 (below the threshold).
Since there are only two levels, the voltage margin between the two levels can be quite high. This makes it is easier and faster to read the cell. The Raw Bit Error Rate (RBER) is also low due to the lower impact of any leakage or disturbances during read operations owing to the larger voltage margin. A low RBER also reduces the number of ECC bits required for a given block of data.
Another advantage of the large voltage margin is that the effect of wear is comparatively less as minor leakage of charges will have relatively lower impact. The wider distribution for each logic level helps the cells to be programmed or erased with lower voltages, which further increases the endurance of the cell, in turn increasing the number of lifetime P/E cycles.
One disadvantage is the higher cost per cell compared to other types of Flash that store more data in the same die area. SLC Flash is often used in applications that are not cost sensitive and require high reliability and durability, such as industrial and enterprise applications with a large number of required P/E cycles.
Multi Level Cell (MLC) NAND Flash
In MLC Flash, each memory cell stores two bits of information, i.e., 00, 01, 10 and 11. The threshold voltage is compared against three levels in this case (total 4 voltage bands).
Figure 3: The voltage in an MLC Flash cell is compared against three threshold voltages to determine its logical two-bit value.
With more levels to compare, the read operation needs to be more precise, making reads slower compared to SLC Flash. The Raw Bit Error Rate (RBER) is also comparatively higher owing to the lower voltage margin, and more ECC bits are needed for a given block of data. The effect of wear is more significant now as any leakage of charges will have a larger relative impact compared to SLC Flash, in turn reducing the number of lifetime P/E cycles.