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Using chip-on-chip SiP techniques in small footprint embedded designs

Mamoru Kajihara and Han Park, NEC Electronics America Inc.

May 11, 2007

Mamoru Kajihara and Han Park, NEC Electronics America Inc.May 11, 2007

The soaring popularity of cellphones and digital still cameras (DSCs) requiring small-form-factor IC packages has spurred considerable interest in system-in-package (SiP) solutions. But SiP isn't just about size.

Because each functional chip can be developed individually, SiP means faster development and lower cost as compared with SoC, which must be developed as one large single-chip design.

As early as 2001, SiP solutions were already being built from functional chips that have been qualified, designed and intended for single-chip packages.

SiP and chip-scale packaging
Essentially designed for chip-scale packaging, these solutions posed a big problem to SiP development: when two chips were stacked, their pads cannot be aligned. Sometimes, the corresponding pads are located on opposite sides of chips, thus requiring signal routing over the interposer.

Connections available with multilayer package interposers have drawbacks, as wires became longer and signal integrity (SI) deteriorated. In addition, package interposer costs increased.

To avoid such disadvantages, design engineers developed SiP chips with pad locations that fit shorter wire connections. For example, memory interface pads are put on the top and bottom, and signal pads that connect to the outer pins are put on the right and left sides of the logic chip.

If the memory chip is rectangular, pads are moved to the shorter sides of the rectangle. The logic chip and the memory chip are then stacked in one direction, connecting the memory chip's shorter line with the logic chip's top and bottom, which have the memory interface pads.

Side-by Side SiP
On the other hand, side-by-side SiP packaging is widely used when combining chips from different wafer processes and generations is needed. For example, a side-by-side SiP in an automotive application might include a signal processor chip made from a logic wafer fabrication process and an actual driver chip made from an analog wafer fabrication process.

In that case, performance and cost of the signal processor could be improved using a new-generation wafer process, while the driver chip would remain in its stable wafer process due to the 12V handling and endurance requirement.

Since new-generation processes cannot handle higher voltages, an SiP approach becomes the prime candidate for this combination. Packaging solutions with both analog and digital functions pose another problem.

If an analog chip includes the signal input receiver or output driver functions, then the signal, amplitude and polarity are controlled first by the digital chip and then through the analog chip. This combination is always a series connection, and usually the analog chip is smaller than the digital chip.

If these combinations assumed a stacked-chip structure, then the analog chip would be put on top of the digital chip. The signal would start from the digital chip pads. It would pass through the analog chip, through the signal wire connecting the package interposer, and then route over both the analog and digital chips. A better selection would be a side-by-side SiP.

Figure 1. A CoC approach with bump connections instead of gold wire connections has been developed to meet the needs of mobile devices.

Chip-on-chip SiP designs
Side-by-side SiP solutions used to look very much like miniature multichip modules, but performance improvements of the original single chip required the addition of subchips. The idea of stacking chips in an SiP came about as a way to decrease the total footprint.

Take DSCs as an example of a recent application that demands both high performance and small size. Current models usually have a 5M pixel sensor. A couple of years ago, sensors were typically 1M pixel, which means that a fivefold increase in performance was required. Moreover, power dissipation needed to be reduced to ensure the longer battery life essential for today's DSCs.

To satisfy these opposing requirements, companies developed a chip-on-chip (CoC) approach that has bump connections (Figure 1, above) instead of gold-wire connections between the logic and memory chips. Because there is no gold wire between the logic chip and memory, the signal data transfer rate is higher.

The CoC approach also dissipates less power and has a dedicated I/O buffer. A general double-data-rate memory bus requires a 2.5V signal swing, 5mA maximum current and 125mW maximum power per signal pad. When the dedicated I/O buffer is applied, a 1.2V signal swing - the same as a conventional 130nm power supply - becomes a suitable option.

Since the I/O buffer load is just a point-to-point connection, one-tenth current can be applied. As a result, operating frequency increases five times, at half the voltage, one-tenth the current and one-fourth the power. One additional benefit is a smaller chip size.

With newer-generation wafer processes for logic chips on the rise and requests for more memory capacity increasing, memory chip size seems to be exceeding logic chip size. This means that there is no exposed pad area to make a connection for the outer pin.

The Association of Super-Advanced Electronics Technologies has described a 3D through-hole stacked structure that can address this problem. With this technology, small logic chips can handle large memory capacity without SI degradation because of the short path between the logic chip and the stacked memory chips in the 3D through-hole substrate.

Development in this area has just begun and new avenues for exploration are abundant. For instance, a designer could choose a logic chip with the same size as a memory chip and stack it along with memory chips using a 3D through-hole substrate. By repeating the logic chip and stacked-memory chip structure, the designer could eventually produce an SiP with "huge-scale" memory.

SiP solutions come in several shapes, including stacked-chip structures that target small for m factors, side-by-side solutions for I/O terminal functional chips, CoCs for high-frequency operation using low power, and 3D through-hole stacked structures for large memory devices.

The main benefit of an SiP had been its short development lead time, but feasibility studies have shown that SiPs can perform like SoCs. In addition, SiPs allow the combination of different wafer process chips in one solution, making them not only a package, but also a true system.

Mamoru Kajihara and Han Park are senior packaging engineering managers at NEC Electronics America Inc.

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