Teaching old dogs new serial I/O tricks on CompactPCI
Even systems that have withstood the test of real-world applications for a decade or more are eventually challenged to keep up with the times. And popular CompactPCI systems used for robust, modular embedded computing system applications in telecommunications, industrial automation, real-time data acquisition, instrumentation and military systems are no exception.
Until recently, CompactPCI systems were limited to a parallel bus and could not take advantage of high-speed serial point-to-point communications. Now, there are two new standards addressing implementation of such capabilities, with each offering a slightly different execution. But both offer similar benefits in terms of expanded high-speed I/O capabilities and performance.
The approved PICMG 2.30 specification for the CompactPCI PlusIO standard provides options for enhancing existing CompactPCI installations with the addition of high-speed serial communications.
It takes advantage of the user pins on the J2 connector that were originally designated for 32-bit system slots as a means to deliver serial signal capabilities, yet still maintains interoperability with existing CompactPCI systems.
This creates the option for a natural migration that still protects the capital investment in existing backplanes and peripheral I/O boards still using parallel bus communications.
The new CompactPCI Serial standard (labeled CompactPCI-S.0), approved in March 2011 by a PICMG sub-committee and announced at Embedded World, addresses new applications for system boards and backplanes. But like CompactPCI PlusIO, it allows the merger of existing CompactPCI parallel bus peripheral boards with new peripheral boards using a point-to-point star architecture capable of faster communication and higher signal density.
Extending the capabilities of existing CompactPCI
CompactPCI PlusIO complements the original basic CompactPCI standard (PICMG 2.0), staying true to most of its mechanical requirements. To maintain reverse compatibility, new CPU boards that support PICMG 2.30 (3U/6U) remain fully compatible to the basic CompactPCI standard without limitations and can also be used in existing CompactPCI systems.
The original CompactPCI standard called for a single 220-pin connector to provide all power, ground, 32-bit, and 64-bit PCI signals. That connector consisted of two halves – the lower half (110 pins) called J1, and the upper half (also 110 pins) called J2. Backplanes used male (pin) connectors and plug-in boards use female (socket) connectors.
User I/O pins were not defined by the PICMG 2.0 standard. In order to support serial communications interfaces, however, CompactPCI PlusIO does identify specific assignments for the J2 connector user pins that were reserved for 32-bit system slots in the original standard. CompactPCI PlusIO uses these I/O signals to provide a variety of popular interface options to the backplane:
* 4 PCI Express x1 links
* 4 SATA
* 4 USB 2.0
* 2 Ethernet 1000Base-T
It can also support four PCI Express type 2 peripheral boards.
Hybrid rack systems are already commercially available with a slot to accommodate an existing CompactPCI PlusIO system board, three slots for existing CompactPCI peripheral boards and four slots devoted to CompactPCI Serial peripheral boards. (Figure 1 below.)
Figure 1. CompactPCI.PlusIO Architecture.