Get more wiggle room in your design’s RMS Phase Jitter budget
Virtually any embedded designer will tell you clock jitter is a moving target, and it’s been that way historically. In short, system and embedded designers continually chase jitter and its ill effects on their designs in the hope that they can significantly minimize it.
That’s a challenging task due to the fact that system data rates are dramatically increasing and timing system requirements are becoming ultra-stringent, thus embedded designers demand that root mean square (RMS) phase jitter be as low as possible. Further, due to ever increasing numbers of battery-operated applications, those designers must carefully scrutinize datasheet specs to assure they’re getting the lowest power consumption accompanying the low RMS phase jitter.
RMS phase jitter is a measure of clock quality in communication systems. For example, the system or embedded designer may deal with a typical protocol like Ethernet or PCI Express (PCIe) stating that the clock quality needs to meet a particular RMS spec. Hence, RMS phase jitter qualifies a clocking device to meet a certain standard.
There are also end points. Every end point will have its own unique jitter requirements. As an example, if an end point is a PCIe end point, it’s going to need a PCIe jitter compliant clock, which is a 1ps RMS jitter requirement for PCIe Gen3 common clock architecture.
Aside from RMS phase jitter, there are several different definitions of jitter. But in general, clock jitter is defined as the deviation of a clock edge from its ideal location, as shown in Figure 1. Getting a good handle on jitter and minimizing it are critical since it plays a key role in a system’s timing budget. In this day and age, with highly demanding system applications and evolving state-of-the-art technologies challenging conventional design practices, jitter and how it is resolved take center stage.
Unfortunately, in most cases, advanced technologies for combating jitter have not been able to keep up with demanding OEM applications. The biggest issues associated with minimizing jitter involve highly unacceptable power consumption and clock generator products offered in either too large a package or in multiple device packages. Given the ever-shrinking printed circuit board (PCB) real estate, savvy embedded designers seek out smaller, singular packaging to comply with basic design requirements.
Hitting the sweet spot
Smaller packaging is indeed a sought-after feature, especially for growing numbers of mobile and portable applications. However, embedded designers want considerably more, and they’re intent on hitting the sweet spot from a power consumption and performance standpoint among the industry’s mid-range clock generator choices. An added bonus is having a product capable of targeting applications ranging from one to 10 Gigahertz (GHz) Ethernet, while meeting all system RMS phrase jitter requirements the designer requires to comply with his/her overall goal.
Aside from the mid-range versions discussed here, there are higher and lower-end clock generators involving major power consumption and jitter performance tradeoffs. For instance, there are lower-end clock generators for clocking systems that don’t have tight RMS jitter requirements. At the other end of the spectrum, there are high-end clock generators consuming higher power and designed for clocking super low jitter requirements like sub-300 fs for 10 Gigabits per second (G), 40G, 100G Ethernet, and fiber channel applications.
Frequency margining on the fly
One more thing -- embedded designers seek the ultimate product in frequency margining. Critically important is the fact that they want their systems to be reliable and robust. They evaluate virtually every parameter of their designs and in so doing, they arrive at certain requirements in terms of specification, and work toward achieving a margin to their specification.
In this regard, most designers require sub-one picosecond (psec) RMS phase jitter performance. In most instances, system designers target one psec RMS phase jitter for one Gigabit per second (Gbps) Ethernet and 10 Gbps Ethernet applications. Many clock generators on the market provide RMS phase jitter performance of one psec or higher.
Consequently, embedded designers are robbed of having an ample amount of margin to their system specification. On the other hand, for example, considerably improved 0.7 psec RMS phase jitter performance from 12 KHz to 20 MHz in a programmable clock generator gives them a 30 percent margin to their system specification, enabling them to have a reliable, robust system.
Leading chipmakers are moving in this direction with integrated and innovative clock generator architectures to reach those new levels of frequency margining. In particular, frequency margining takes on a more streamlined approach.
In this case, embedded designers are looking at changing and increasing clock frequency to determine system robustness for a variety of applications including high-performance consumer, networking, industrial, computing, medical electronics, broadcast video, and data communications.
Normally, with current and earlier generation competitive clock generators, to achieve frequency margining, designers tediously have to go from one clock to another and then to another to change frequency, thus consuming extra design time. However, today’s embedded designer requirements are focused on having multiple different output frequencies and multiple different output types in a single packaged clocking device to effectively meet board space and jitter requirement.
For example, as shown in Figure 2, IDT’s 5P49V5901ANLGI programmable clock generator hands embedded designers four totally independent frequencies with four totally independent output types and a reference output – all integrated on one chip.
Figure 2: The VersaClock 5 programmable clock generator (5P49V5901ANLGI) provides designers with four independent frequencies, four independent output types, and reference output in single 4x4 QFN.
The four universal output pairs produce independent frequencies up to 350 MHz, configurable as high-speed current steering logic (HCSL), low-voltage positive emitter-coupled logic (LVPECL), low-voltage differential signal (LVDS), or split into two low-voltage CMOS (LVCMOS) outputs (Figure 3).
Figure 3: Four universal output pairs produce independent frequencies up to 350 MHz configurable as HCSL, LVPECL, LVDS, or LVCMOS outputs.
The clock generator takes in a single fundamental crystal or reference clock input, generates the four high frequency outputs, and supports from 5 to 350 MHz with 0.7 psec RMS phase jitter.