Reliable systems for micro aerial vehicles -- Supply resilience
Editor's Note: Embedded designers must contend with a host of challenges in creating systems for harsh environments. Harsh environments present unique characteristics not only in terms of temperature extremes but also in areas including availability, security, very limited power budget, and more. In Rugged Embedded Systems, the authors present a series of papers by experts in each of the areas that can present unusually demanding requirements. A separate excerpt of the book addresses fundamental concerns in reliability and system resiliency.
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Adapted from Rugged Embedded Systems, Computing in Harsh Environments, by Augusto Vega. Pradip Bose, Alper Buyuktosunoglu.
CHAPTER 7. Reliable electrical systems for micro aerial vehicles and insect-scale robots: Challenges and progress (Cont.)
By X. Zhang, Washington University, St. Louis, MO, United States
5 SUPPLY RESILIENCE IN MICROROBOTIC SoC
Among the numerous challenges surrounding the SoC design for microrobotic applications, reliability, and performance of the system in the presence of supply noise is one critical problem to be addressed. Similar to many integrated computing systems, a microrobotic SoC employs synchronous digital logics in its central control unit and thus is susceptible to disturbance on the supply voltage.
However, the crucial weight and form factor constraints set the microrobotic SoC apart from conventional systems. Given the extremely stringent weight budget, extra external components must be avoided at all cost, which leads to the integration of on-chip DC-DC converter and the absence of external frequency reference. With such IVRs powered directly off a discharging battery, the microrobotic SoC experiences supply-noise characteristics different from conventional digital systems, where existing supply-noise mitigation techniques cannot be easily applied.
In this section, we describe how an adaptive-frequency clocking scheme is used in our BrainSoC design to exploit the synergy between IVR and clock generation. The resulting supply-noise resilience and performance improvement has been demonstrated by a prototype SoC developed prior to the BrainSoC . Our proposed adaptive clocking scheme not only delivers better reliability and performance, but also extends the error-free operation to a wider battery voltage range, which is beneficial to a microrobotic system.
SIDEBAR: BACKGROUND ON SUPPLY NOISE
Digital computing systems based on synchronous logic circuits typically employ a fixed frequency clock. To guarantee correct operation, final outputs from the datapath must arrive at the next flip-flop stage before the next clock edge by some time margin known as the “setup time”. Since the datapath delay is a function of the supply voltage, it is susceptible to noise on the supply line.
Supply noise is the result of nonideal power delivery system and load current fluctuation under varying computation workload. It can come from the parasitic resistance, inductance, and capacitance in the power delivery network, and manifests itself as static IR-drop, which is the static voltage drop due to power grid resistance, as well as dynamic L di/dt drop, which is the transient voltage fluctuation caused by the inductance and capacitance in response to load current changes. Also, for systems with integrated switching regulators, the intrinsic voltage ripple of the regulator contributes additional noise to the supply. The existence of supply noise can modulate the datapath delay, which may lead to setup time margin violation and eventually computation errors. In order to ensure sufficient delay margins under all operating conditions, the most straightforward approach is to lower the clock frequency and provide a “guardband” to tolerate even the worst supply-noise scenario.
SIDEBAR: SUPPLY RESILIENCE IN CONVENTIONAL COMPUTING SYSTEMS
Conservative design strategy such as timing guardband is the most commonly applied to combat supply-noise in conventional computing systems. It may incur hefty performance loss and thus is highly undesirable. Instead, a number of alternative techniques have been proposed to mitigate supply-noise with less performance penalty. The active management of timing guardband  in a prototype IBM POWER7 processor is an example of adaptive clocking: a digital phase-locked loop (DPLL) adjusts the processor core’s clock frequency based on the timing guardband sensed by a critical path timing monitor . Since resonant noise caused by the LC tank between the package inductance and the die capacitance has been identified as the dominant component of supply noise in high-performance microprocessors , many studies have focused on this particular type of supply noise by proposing adaptive phase-shifting PLL  and clock drivers . Following the duality between the clock frequency and the supply voltage in synchronous digital systems, the other approach to optimize performance in the presence of supply noise is adaptively adjusting the voltage level delivered by the power supply at different desirable operating frequency. Despite their different implementations, both adaptive clocking and adaptive supply are along a similar vein of technical route that applies closed feedback loop to adjust frequency and/or supply based on monitored timing margin of the system, and therefore are subject to the bandwidth limitation of the feedback loop.
In addition to the above-mentioned systems and techniques, there exist other classes of logic implementations such as asynchronous logics and self-timed logics  that do not rely on a global clock for their operations. Unlike synchronous logics, these systems are intrinsically delay-insensitive and thus immune from the negative impact of supply noise. However, these logic implementations lack the full support of standard libraries, IPs, and EDA tools and thus are difficult to incorporate into the digital design flow of a sophisticated SoC.
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