Reliable systems for micro aerial vehicles -- SoC evaluation
Editor's Note: Embedded designers must contend with a host of challenges in creating systems for harsh environments. Harsh environments present unique characteristics not only in terms of temperature extremes but also in areas including availability, security, very limited power budget, and more. In Rugged Embedded Systems, the authors present a series of papers by experts in each of the areas that can present unusually demanding requirements. A separate excerpt of the book addresses fundamental concerns in reliability and system resiliency.
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Adapted from Rugged Embedded Systems, Computing in Harsh Environments, by Augusto Vega. Pradip Bose, Alper Buyuktosunoglu.
CHAPTER 7. Reliable electrical systems for micro aerial vehicles and insect-scale robots: Challenges and progress (Cont.)
By X. Zhang, Washington University, St. Louis, MO, United States
5.4 PROTOTYPE SoC EXPERIMENTAL EVALUATION
To demonstrate improved resilience and performance of our proposed adaptive clocking across a wide range of supply voltage, measurement results were obtained from the prototype SoC chip (Fig. 12) fabricated in TSMC’s 40 nm CMOS technology. We use the maximum error-free operating frequency of the memory performing BIST as a proxy metric, because it is often the on-chip SRAM sharing the same voltage domain with the digital logic that limits the system performance at lower supply levels. Also, the retention voltage of the SRAM cells typically determines the minimum operating voltage of the system .
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FIG. 12 Die photo of the fully integrated prototype system-on-chip.
First, we characterize the voltage versus frequency relationship of the SRAMs using external sources in order to determine the efficacy of using the DCO for adaptive-frequency clocking. Then, we compare the fixed- and variable-frequency clocking schemes with a regulated voltage generated by the SC-IVR in closed-loop operation. Lastly, we present the advantages of combining adaptive clocking with a variable voltage provided by operating the SC-IVR in open loop.
5.4.1 Frequency versus voltage characterization
The on-chip SRAMs were characterized at static supply voltage levels provided externally via EXTVDD, in order to determine the SRAM’s voltage to frequency relationship under quiet supply conditions. Using an external clock (EXTCLK) at different fixed frequencies, we obtained the Shmoo plot in Fig. 13A. It shows (1) the minimum retention voltage of SRAM cell is between 0.6 and 0.65 V; (2) the maximum SRAM frequency scales roughly linear with supply voltage and ranges from 68 at 0.65 to 256 MHz at 1.0 V; and (3) the maximum SRAM frequency closely correlates with DCO frequency plot for control code D1⁄410. This correlation suggests the FO4-delay-based DCO tracks the critical path delay in the SRAM across a wide supply range and should enable error-free memory BIST for control word D above 10. We experimentally verified this by turning on the internal DCO to provide the system clock instead of using EXCLK and sweeping the same voltage range via EXTVDD. The resulting Shmoo plot in Fig. 13B further demonstrates the DCO’s ability to track SRAM delay at different static supply voltage levels. Considering process and temperature variations, the same control word D1⁄410 may not apply to chips from all process corners and over all temperature ranges. However, since the process and temperature conditions are relatively static, and our results show that a fixed control word can cover the range of fast-changing supply variation, it is possible to determine this fixed control word during the calibration phase before the normal operation of the robotic system starts.
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FIG. 13 Shmoo plots for two different clocking schemes. (A) External clock at fixed frequencies and (B) internal adaptive clock generated by the DCO at different control code D.