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High-performance embedded computing -- Power and energy consumption

João Cardoso, José Gabriel Coutinho, and Pedro Diniz

February 04, 2018

João Cardoso, José Gabriel Coutinho, and Pedro DinizFebruary 04, 2018

Table 2.1 presents an example of four OOPs of a hypothetical processor. This example considers the processor can operate with a supply voltage of 1 V at a maximum clock frequency of 300 MHz, or 1.2 V at 600 MHz, or 1.3 V at 800 MHz, or at 1.4 V at 1 GHz. These OOPs can be managed by the operating system (OS) and/or by the application via system library functions.

To reduce dynamic power and static power consumption, two main mechanisms can be used, namely, dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM), respectively. These two techniques are described in the following subsections.


Table 2.1 Example of frequency-voltage table (representing OPPs)

The energy consumed, represented in Joules (J), during a period of activity is the integral of the total power dissipated (Eq. 2.6 for CMOS ICs) over that period. Eq. 2.11 represents in a simplified way the total of energy consumed during a period T (in seconds) as the product of the average power dissipated over that period (Pavg) by T. For a given application, one can save energy if power consumption/dissipation is reduced and the execution time is not increased as much, or conversely if the execution time is reduced without a large increase in power dissipation.

ACPI: ADVANCED CONFIGURATION AND POWER INTERFACE

ACPIa is a standard interface specification supported by hardware and software drivers. Usually the operating system uses this API to manage power consumption, but the API can also be used by applications.

ACPI considers four global states (from G0 to G3, with a subdivision in six sleep states S0 to S5), performance states (base on the possible OPPs), known as P-states (and from P0 to P15 at maximum, being P0 the state operating at maximum clock frequency and resulting in the highest power dissipation), Processor states, known as C-states (and usually from C0 to C3, but depending on the processor). The C-states represent operating (C0), Halt (C1), Stop-Clock (C2), and Sleep (C3) states.

a Unified EFI Inc. Advanced configuration and power interface specification ACPI overview. Revision 5.1 [July, 2014] http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf.

Energy consumption is not directly associated with heat but affects battery usage. Thus by saving energy one is also extending the battery life or the length of the interval between battery recharges. On the other hand, energy efficiency is a term related to performing the work needed with as less energy as possible, sometimes being quantified by the work done per Joule (e.g., samples/J, Gbit/J, and frames/J). Two common metrics used to represent the trade-off between energy consumption and performance are the energy delay product (EDP) and the energy delay squared product (ED2P). EDP is obtained by multiplying the average energy consumed by the computation time required [31]. Both EDP and ED2P give more importance to the execution time than to the energy consumed. Compared to EDP, by squaring the computation time required, the ED2P metric gives even more importance to execution time than to energy consumption. One can give even more importance to performance by powering the computation time required by values >2.

The next installment in this series discusses dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM).  

Reprinted with permission from Elsevier/Morgan Kaufmann, Copyright © 2017


João Manuel Paiva Cardoso, Associate Professor, Department of Informatics Engineering (DEI), Faculty of Engineering, University of Porto, Portugal. Previously I was Assistant Professor in the Department of Computer Science and Engineering, Instituto Superior Técnico (IST), Technical University of Lisbon (UTL), in Lisbon (April 4, 2006- Sept. 3, 2008), and Assistant Professor (2001-2006) in the Department of Electronics and Informatics Engineering (DEEI), Faculty of Sciences and Technology, at the University of Algarve, and Teaching Assistant in the same university (1993-2001). I have been a senior researcher at INESC-ID (Systems and Computer Engineering Institute) in Lisbon. I was member of INESC-ID from 1994 to 2009.

José Gabriel de Figueiredo Coutinho, Research Associate, Imperial College. He is involved in the EU FP7 HARNESS project to intergrate heterogeneous hardware and network technologies into data centre platforms, to vastly increase performance, reduce energy consumption, and lower cost profiles for important and high-value cloud applications such as real-time business analytics and the geosciences. His research interests include database functionality on heterogeneous systems, cloud computing resource management, and performance-driven mapping strategies.

Pedro C. Diniz received his M.Sc. in Electrical and Computer Engineering from the Technical University in Lisbon, Portugal and his Ph.D. from the University of California, Santa Barbara in Computer Science in 1997. Since 1997 he has been a researcher with the University of Southern California’s Information Sciences Institute (USC/ISI) and an Assistant Professor of Computer Science at the University of Southern California in Los Angeles, California. He has lead and participated in many research projects funded by the U.S. government and the European Union (UE) and has authored or co-authored many internationally recognized scientific journal papers and over 100 international conference papers. Over the years he has been heavily involved in the scientific community in the area of high-performance computing, reconfigurable and field-programmable computing.

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