High-performance embedded computing -- Dynamic voltage and frequency scaling
Dynamic frequency scaling (DFS) and dynamic voltage scaling (DVS) are techniques to reduce the power dissipation when voltage and frequency ranges are not fully interdependent, i.e., when changes in clock frequency do not imply (up to a certain point) changes in the supply voltage and vice versa. Decreasing the clock frequency without changing the supply voltage (possibly maintaining it to the level needed to operate at the maximum clock frequency) implies a decrease of power dissipation but may lead to insignificant changes in energy consumption (theoretically we would expect the same energy consumption). Decreasing the supply voltage without changing the operating frequency implies both power and energy reductions.
The DVFS technique can be seen as a combination of DFS and DVS and when the interdependence between power supply and operating frequency is managed in a global way. However, in CPUs where the voltage-frequency interdependence exists, DFS, DVS, and DVFS are often used with the same meaning, i.e., the dynamic scaling of voltage-frequency.
2.6.3 DARK SILICON
The end of Dennard scaling , which argued that one could continue to decrease the transistor feature size and voltage while keeping the power density constant, has raised a big challenge for large transistor count IC designs. At the core of the issue of power density is the fact that with the growing number of increasingly smaller transistors, the aggregate leakage current, if unchecked, is large enough to create the threat of thermal runaway. This is particularly serious in devices with many cores where the execution of all the cores at maximum or acceptable speed is unfeasible.
To cope with this issue, ICs may have resorted to “Dark Silicon”  techniques that under-power or under-clock regions of an IC whenever they are not being used. To support these techniques, ICs have to provide low-level mechanisms that allow the monitoring of the thermal conditions of specific regions of the IC, e.g., of a coprocessor or hardware accelerator and provide an interface with which a runtime environment or a scheduler can reduce the associated clock rate or even temporarily power down that unit for the sake of power dissipation. The impact on the ability of compilers to statically schedule the execution of selected computations on such devices is substantial. Execution predictability and hence nonfunctional requirements guarantees such as latency and throughput are, in this context, harder to ensure. Another possibility is to map and schedule the computations at runtime using OS, middleware, or application-level support.
The next installment in this series discusses factors that arise in comparing results of the methods described previously.
Reprinted with permission from Elsevier/Morgan Kaufmann, Copyright © 2017
João Manuel Paiva Cardoso, Associate Professor, Department of Informatics Engineering (DEI), Faculty of Engineering, University of Porto, Portugal. Previously I was Assistant Professor in the Department of Computer Science and Engineering, Instituto Superior Técnico (IST), Technical University of Lisbon (UTL), in Lisbon (April 4, 2006- Sept. 3, 2008), and Assistant Professor (2001-2006) in the Department of Electronics and Informatics Engineering (DEEI), Faculty of Sciences and Technology, at the University of Algarve, and Teaching Assistant in the same university (1993-2001). I have been a senior researcher at INESC-ID (Systems and Computer Engineering Institute) in Lisbon. I was member of INESC-ID from 1994 to 2009.
José Gabriel de Figueiredo Coutinho, Research Associate, Imperial College. He is involved in the EU FP7 HARNESS project to intergrate heterogeneous hardware and network technologies into data centre platforms, to vastly increase performance, reduce energy consumption, and lower cost profiles for important and high-value cloud applications such as real-time business analytics and the geosciences. His research interests include database functionality on heterogeneous systems, cloud computing resource management, and performance-driven mapping strategies.
Pedro C. Diniz received his M.Sc. in Electrical and Computer Engineering from the Technical University in Lisbon, Portugal and his Ph.D. from the University of California, Santa Barbara in Computer Science in 1997. Since 1997 he has been a researcher with the University of Southern California’s Information Sciences Institute (USC/ISI) and an Assistant Professor of Computer Science at the University of Southern California in Los Angeles, California. He has lead and participated in many research projects funded by the U.S. government and the European Union (UE) and has authored or co-authored many internationally recognized scientific journal papers and over 100 international conference papers. Over the years he has been heavily involved in the scientific community in the area of high-performance computing, reconfigurable and field-programmable computing.