Finding angle resolution of resolver-to-digital converters
A resolver is a sensor that estimates the angle of a rotating shaft, such as the shaft of an electrical motor used in automotive traction inverter applications. To obtain a digital representation of the rotating shaft angle, resolvers interface with sensor signal-conditioning circuits called resolver-to-digital converters (RDCs). In this article, we determine the angle resolution of RDCs based on the common all-digital phase-locked loop (ADPLL) architecture. This formula for angle resolution readily shows the design parameters that influence the accuracy of the shaft angle estimated by the RDC.
Resolver-to-digital converters (RDCs) are signal conditioning circuits that are used to obtain a digital representation of the angle of a rotating shaft. This angle estimate is used in servo applications as well as electrical commutation of motors. To obtain angle estimates, RDCs excite the resolver primary coil and process the output of the resolver secondary coil. Specifically, RDCs use a digital processing technique to extract the shaft angle from amplitude of the secondary coil and represent the angle in digital format for use in control algorithms .
A commonly-used digital processing technique for implementing RDC is the all-digital phase-locked loop (ADPLL) architecture. A phase-locked loop (PLL) is a very versatile, popular architecture that has been around for several decades . In this article, we determine the angle resolution of RDCs that are based on ADPLL. Furthermore, we show the effect of RDC design parameters on the angle accuracy of ADPLL-based RDCs.
Figure 1 shows a block diagram representation of an ADPLL architecture  with the following components:
- A phase detector (PD)
- A loop filter (LF)
- A digitally controlled oscillator (DCO)
Figure 1: Block diagram representation of an APDLL architecture where r(t) is the reference oscillation signal, PD is the phase detector, LF is the loop filter, DCO is the digitally controlled oscillator and y(t) is the output oscillation signal.
APDLL architecture for an RDC
In the context of modeling and analyzing the RDC, we made specific choices for each of the components shown in the ADPLL block diagram shown in Figure 1. The following subsections describe these choices.
There are many forms of phase detectors. We chose an exclusive-OR (XOR)-type phase detector, symbolically represented in Figure 2.
For the reference signal r(t), we used the squared version of the resolver’s primary excitation sinusoid signal, as represented by Equation 1:
where f is the frequency of the excitation signal in hertz. At any given point in time, r(t) takes a value of either +1 or –1, depending on the magnitude of the excitation signal. A comparator can convert the sinusoid primary excitation signal into a square signal.
Figure 2: Symbolic representation of an XOR phase detector.
Since r(t) takes a value of either +1 or –1, and assuming that y(t) also takes a value of +1 or –1, it is clear that the XOR output e(t) will also take a value of +1 or –1. The output of the XOR is a sequence of pulses, as shown in Figure 3.
Figure 3: The signal output of an XOR phase detector. The output is +1 if r(t) and y(t) have different values, while the output is –1 if r(t) and y(t) have the same values.
Figure 4 shows the normalized average error of the XOR PD. You can see that the average output of the PD increases as the phase difference between r(t) and y(t) increases from 0 to π, and decreases as the phase difference increases from π to 2π.
Figure 4: Average of the XOR PD output.
Once again, there are many types of LFs that you can use in a PLL. As in reference , we used a proprotional+integral (PI)-type loop filter (see Figure 5).
Figure 5: Block diagram representation of a PI loop filter.
Equation 2 gives the z-domain transfer function of the PI loop filter as:
where KP and KI are the proportional and integral constants of the PI loop filter, respectively.
Since e(t) takes a value of either +1 or –1, the proportional output would be +KP or –KP. On the other hand, the integral output is the accumulation of +KI or –KI over time.
So what is the significance of the output of the LF? We can answer this question by understanding how a DCO works. We will explore this in the next section.
Note that the PI loop filter has one pole on the unit circle.
Continue to page two on Embedded's sister site, EDN: "Determining the angle resolution of all-digital PLL-based resolver-to-digital converters."