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Using clock generators/buffers to adapt your PCIe design to specific application needs

Kyle Beckmeyer, Silicon Labs

June 02, 2013

Kyle Beckmeyer, Silicon LabsJune 02, 2013

The PCI Express (PCIe) interconnect has grown popular over the past five years and is now widely used in many different markets and applications. Originally developed for use in the personal computing (PC) and server markets, the PCIe standard has become a de facto data bus used in communications, storage, industrial, and consumer electronics products.

Although the performance requirements for PCIe reference clocks are standard within any application, numerous clock generator and buffer products optimized for PCIe are available to help systems designers address the unique requirements of consumer, server/storage, and communications applications.

A PCIe data link (Figure 1) consists of one or more lanes encompassing a transmit (Tx) and receive (Rx) differential pair. A PCIe slot may contain up to 32 lanes, providing excellent bandwidth scalability. The first-generation PCIe specification was introduced by the PCI-Special Interest Group (SIG) in 2003, with a maximum data throughput of 16 GBytes per second (GB/s) in a 32-lane configuration. At the time, this specification was a major improvement over the previously used PCI and PCI-X bus architectures. Four years later, the PCIe 2.0 spec was released, which doubled the transfer rate to 32GB/s in a 32-lane configuration. This effectively meant designers could get the same amount of data transfer bandwidth in half the lanes of a Gen1 based design. The PCI-SIG introduced the third-generation specification in November 2011, again doubling the transfer rate to 64 GB/s.




Figure 1: The PCI Express Link

Market trends fueling PCIe adoption
In 2007, PCIe Gen2 had become widely used in most server/storage and communications infrastructure applications. At the same time, PCIe Gen1 started gaining traction in the embedded, instrumentation, and customer premises equipment (CPE) markets. The need for higher data throughput, an attractive cost point, scalability, and growing availability of PCIe ports in SoCs, ASICs, microprocessors, and FPGAs were all contributing factors in PCIe Gen1 proliferation into these markets. Multi-function printers, network switches, routers, wireless access points, and high-end consumer electronics were all starting to adopt PCIe as larger amounts of digital data were being created and used by consumers.

Although the consumer electronics market had not yet adopted the PCIe interconnect, it was fueling the requirement for PCIe to continue scaling towards higher data rates and larger bandwidth capability. By early 2008, smartphone adoption and social media were both rapidly growing in popularity, enabling end users to not only create, store, and share new digital media content such as pictures and video but also to request access to that content anywhere and anytime via the Internet and cellular devices.

At the same time, cloud computing and audio/video streaming services were becoming popular with consumers. Furthermore, Internet-based high-definition music and video services were becoming mainstream, increasing demand for higher bandwidth capability from server and datacenter infrastructure. Consumer thirst for high-resolution media content was requiring more bandwidth at faster speeds.

These market trends led to the adoption of the PCIe Gen3 interconnect standard, which has been predominantly used in server, storage, and datacenter end markets to date. New technology advancements in solid state drive (SSD) devices have further enabled datacenter and cloud computing to keep up with consumer demand for digital content. Enterprise SSDs use PCIe Gen3 as the main interconnect between the host motherboard and SSD controllers, enabling incredibly fast access to content stored in datacenters and in the cloud.

By using PCIe Gen3, networking and enterprise equipment manufacturers have been able to scale bandwidth and data rates without rebuilding the entire infrastructure. As with the previous generation shift from PCIe Gen1 to PCIe Gen2 in the 2007 time frame, PCIe Gen2 is now becoming widely adopted in the embedded, communications, and CPE markets. PCIe Gen2 ports are now commonly found in general-purpose microprocessors, FPGAs, SoCs, and ASICs.

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