Making efficient use of BGA signal routing in PCB designs

Faisal Ahmed and Ishtiaq Safdar, NexLogic Technologies

January 25, 2015

Faisal Ahmed and Ishtiaq Safdar, NexLogic TechnologiesJanuary 25, 2015

Ball grid array (BGA) device packaging is today’s standard for housing a range of highly advanced and complex semiconductor devices like FPGAs and microprocessors. The technology of BGA packaging for embedded designs is steadily advancing to keep up with chipmaker technical advances, with this type of packaging splintering out into standard and micro BGAs. Today, both types deal with increasing numbers of I/Os, and this means signal escape routing is difficult and challenging, even for experienced printed circuit board (PCB) and embedded designers.

The top job for the embedded designer is to develop appropriate fan-out strategies that won’t adversely affect board fabrication. There are several major considerations involved in selecting the correct fan-out/routing strategy: ball pitch, land diameter, number of I/O pins, via types, pad size, trace width and spacing, and the number of layers required to escape the BGA.

PCB and embedded designers will always be challenged to use the minimum number of board layers. The number of layers needs to be optimized to reduce cost. But sometimes a designer must rely on a certain number, for example, to suppress noise by sandwiching actual routing layers between ground plane layers.

Figure 1: Dog bone fan-out

Aside from those design factors inherent in particular BGA-based embedded designs, a major portion of the design involves two basic methods the embedded designer has to perform to correctly escape signal traces from a BGA: dog bone fan-out (Figure 1) and via-in-pad (Figure 2). Dog bone fan-out is used for BGAs with 0.5 millimeter (mm) and above ball pitch, while via-in-pad is used for BGAs and micro BGAs with below 0.5 mm ball pitch, also known as ultra-fine pitch. Pitch is defined as the spacing between the center of one BGA ball to the center of the next one.

Figure 2: Via in pad fan-out

It’s important to know some basic terminology associated with these BGA signal routing techniques. The term “via” is the most prominent. It refers to a pad with a plated hole connecting copper tracks from one PCB layer to other layers. High-density multi-layer boards may have either blind or buried vias, also known as micro-vias. Blind vias are visible only on one surface; buried vias are visible on neither surface.

Dog bone fan-out
Dog bone BGA fan-out provides partitioning into four quadrants with a wider channel in the middle of the BGA to run multiple traces from inside. Several key steps are involved to break out signals from the BGA and connect them to other circuitry.

The first step is to determine the via size needed for the BGA fan-out. Via size depends on a number of factors -- device pitch, PCB thickness, and the number of traces to be routed from one area of the via or one perimeter to the next. Figure 3 shows three different perimeters associated with a BGA. A perimeter is the boundary of a polygon is defined in a shape of a rectangle or square surrounding the BGA balls.

Figure 3: Three different perimeters associated with a BGA

Consider an imaginary line going through the first row (horizontally) and first corresponding column (vertically) comprising the first perimeter, and again for the second and third perimeter. A designer starts off routing the outer perimeter of the BGA, then moving inward, and, in the end, toward the inner-most perimeter of the BGA balls. Via size is calculated using land diameter and ball pitch, as shown in Table 1. The land diameter is the diameter of the pad of each BGA ball.

Table 1: Calculating via size using land diameter and ball patch

Once the dog-bone fan-out is done and the particular via pad size is determined, step two is to define trace width for traces coming into the board’s internal layers from the BGA. A number of factors go into confirming trace width. Table 1 shows that trace width. Minimum space required between traces define a BGA’s escape routing. It’s important to know that reducing spacing between traces increases board fabrication cost.

The area between two vias is called a channel for running the traces. The channel area between adjacent via pads is the smallest area through which the signal must be routed. The number of traces that can be routed through this area is calculated using Table 1.

As Table 1 shows, performing BGA signal escape routing is defined by trace width and the minimum space required between traces. The channel area between adjacent via pads is the smallest area through which the signal must be routed.

Channel area CA= BGA pitch - d, where d is the via pad diameter.

The number of traces that can be routed through this area is calculated using Table 2.

Table 2: Calculating the number of traces through a given channel area.

A number of traces can be routed through various channels. For example, one or two traces can be routed and sometimes three if BGA pitch isn’t very fine. For instance, with a one-millimeter pitch BGA, multiple traces can be routed. However, with today’s advanced PCB designs, most often only a single trace is routed through a channel.

Once the embedded designer has determined trace and space width, the number of traces routed through one channel, and type of via to be used for the BGA layout, he or she can estimate the number of layers that will be required. Use of fewer I/O pins than the maximum can reduce the number of layers. If routing on primary and secondary side is allowed, then the two outer perimeters can be routed without using vias. The next two perimeters can be routed on the bottom side.

At step three, the designer keeps impedance matching as required and determines the number of routing layers to be used to completely breakout the signals from the BGA. Next, he or she routes the BGA’s outer periphery using the top board layer or the same layer where the BGA is placed.

The remaining inner parameters are distributed among internal routing layers. Depending on the number of traces routed internally within each channel, a fair estimate is made on the number of layers required to completely route the BGA.

Once the outer periphery is routed, the next periphery is routed. The set of images in Figure 4a and Figure 4b illustrate how a PCB designer routes different BGA peripheries, starting from the outermost and moving to the center. The first image shows how the first and second inner periphery is routed. Subsequent internal peripheries are similarly routed until the BGA is completely routed.

Figures 4a and 4b: How to route different BGA peripheries, starting from the outer most and moving to the center.

In some designs where electro-magnetic interference (EMI) is a concern, the external layer or top layers aren’t used to route even the outer periphery. In that case the top layer is used for a ground plane. EMI includes the susceptibility of a product to fields from the outside world that couple in and radiate emissions from a product, which causes it to fail compliance tests. A product is considered EMC compliant if it satisfies three criteria:
  • It doesn’t interfere with other systems
  • It’s not susceptible to emission from other systems
  • It doesn’t cause interference with itself.

To prevent the product from transmitting and receiving undesired signals, it’s recommended that the product be shielded. Shielding generally refers to a metallic enclosure that completely encloses an electronic product or portion of product. However, in most cases having the outer layers filled with ground plane serves the shielding purpose as it absorbs energy and minimizes interference.

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