One of the perks of being editor of EET/Embedded.com is that I often get a chance to review papers and materials for classes at various technology conferences ahead of time. Out of the more than 80 papers that I read in my review of the classes to be presented at DesignCon 2011, Jan. 31- Feb. 3 , I chose the 11 below as my Editor’s Top Picks for must-attend classes:
“[5 – TA1] Embedded Active Parts: how, when and who,” by Per Viklund, goes into detail on how many large electronics companies reduce costs on their high volume printed circuit board designs using what is called “active parts,” which at its simplest involves embedding active devices, not just passives, into the many nooks and crannies between components and modules on a PCB and doing it in ways that reduce costs, improve reliability, and may actually make such designs harder to copy.
“[1 – TP5] A Flexible Interconnect Architecture for System Designers,” taught by Aaron Ferrucci and Kent Orthner, in which they describe the Qsys Network On Chip interconnect architecture that Altera has developed, as well as a system-level design tool to implement system transactions amongst programmable elements. In addition to the interconnect, the architecture has a number of features designed to support high performance operation on FPGAs, including a packet format tailored to each particular system's needs, and a network topology that separates command and response networks for higher concurrency and lower resource cost.
“[2 – WA1] Breaking through the Analog IC Layout Design Bottleneck ,” taught by Jeff Miller, John Zuk and Ciaran Whyte, in which they present a new paradigm for addressing the analog design layout bottleneck through the use of a high performance device generator (HiPer DevGen). Rather than try to automate the process of integrating digital and analog portions of a system-on-chip design, they use a new approach that provides layout acceleration as an alternative to automation. It offers automatic generation of design primitives with no change in design flow methodology required. The result is that development cycle times are dramatically reduced – with the tool generating high quality “first time right” layouts. Users retain complete control over the design – with no change in design flow methodology.
“[6 – WP5] Novel I/O modeling for PI analysis on PCB , ” presented by Remco de Jager, in which he will describe a simpler way to use alternative to traditional Power Integrity (PI) simulation techniques, which require accurate I/O models. It involves the use of a simple yet accurate 4-terminal on-chip I/O model containing five parameters that are derived from the IBIS file description. It will allow PCB designers to perform a full PI/SI analysis on high-speed single-ended memory systems and optimize their supply decoupling configurations.
“[7 – WP6] High Speed Parallel Signal Crosstalk Cancellation Concept ,” presented by Chad M. Smutzer, where he describes a new technique he and fellow engineers at the Mayo Clinic use for dealing with crosstalk due to tightly couple transmission lines in systems with high density, parallel I/O. The crosstalk cancellation signaling concept uses the known, predictable theory of coupled transmission lines to cancel crosstalk from neighboring traces with carefully chosen resistive cross-terminations between them. Through simulation and analysis of practical bus architectures, they describe how it can be used in dense interconnect HPC (or other) applications.
“[4 – TA1] A Way to Meet Bandwidth and Capacity Needs of Next Generation Main Memory System,” a class in which Ravi Kollipara describes how he and fellow engineers at Rambus have developed a set of proprietary techniques to raise the data rates of nextgen single-ended main memory systems to 1600-3200 Mbps range without sacrificing memory capacity, increasing power consumption.
“[1 – WP6] EDA Tool Integration and Multi-Paradigm Design Analysis,” presented by Mentor Graphics Chief Architect Fector Pikus, details the motivation and the need for integrating different EDA tools into complex flows. The class reviews the history of the tool integration and the lessons to be learned from the previous attempts. He also shows us what progress is being made toward new forms of multi-domain design analysis and verification that will make possible a combined hardware/software design flow that is more than the sum of its component parts.
In addition to these classes and papers, several others I liked and chose to be featured on Embedded.com are:
[3 – WA3] Case study of PID control in an FPGA
[3 – TH1] Hardware-based floating point design flow
[10 – WA3] Multiband architecture for highs-speed SerDes
[4 – TA4] Using codesign to optimize system interconnect paths
If you attend DesignCon, let me know what you think about my choices and what other papers and classes you found interesting and why, either by leaving comments at the end of this article or by contacting me directly. (EET/Embedded.com Editor Bernard Cole, , 928-525-9087 )