DesignCon 2013: Signal integrity in serial interconnect designs -

DesignCon 2013: Signal integrity in serial interconnect designs

To ensure that you have the most up-to-date knowledge about building the high-speed interconnections in your embedded designs the place to be this month is the 2013 DesignCon, January 28 to 31 at the Santa Clara Convention Center.

Over the period of the four-day conference, one of the main design tracks is “Modeling High-Speed Interconnects for the Signal Integrity Engineer: Tips, Tricks and Trade-Offs.”

All tracks are listed here.

Classes include: 

Monday, January 28:
Challenges and Solutions in Characterizing a 10Gb Device (Agilent)
PCI Express 3.0 Characterization, Compliance, and Debug for Signal Integrity Engineers (Teledyne LeCroy)

Tuesday, January 29:
Synchronous Time and Frequency Domain Measurements Using a Digital Oscilloscope (Rohde & Schwarz)
Ensuring Validation & Analysis of Complex Serial Bus Link Models (Tektronix)
USB 2.0 Compliance Testing (Rohde & Schwarz)
Phase Noise and Jitter Measurements (Rohde & Schwarz)
True Differential S-parameter Measurements / Rohde & Schwarz
Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB (CST of America Inc.)

Wednesday, January 30 :
Making DDR4 Work For You (Agilent)
Debugging to Find the Root Cause of Compliance, Limit or Mask Test Violations (Teledyne LeCroy)

To attend, go to the conference registration page. Options range from an All-Access Pass to Free Expo Admission, which includes choosing to attend one or more dozen tech training sessions. Site Editor Bernard Cole is also editor of the twice-a-week newsletters as well as a partner in the TechRite Associates editorial services consultancy. He welcomes your feedback. Send an email to , or call 928-525-9087.

See more articles and column like this one on up for the newsletters . Copyright © 2013 UBM–All rights reserved.

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