DesignCon, the conference for all things relating to high-speed digital design and test, has issued the 2015 Call for Abstracts. Deadline for submitting your abstracts is July 11, 2014.
DesignCon 2015 will take place in Santa Clara, Calif., January 27 to January 30. Abstracts for technical papers, tutorials, and panel sessions can cover any of 14 tracks:
- Optimize Chip-Level Designs for Signal and Power Integrity
- Overcome Analog and Mixed-Signal Modeling and Simulation Challenges
- Wireless and Photonic Integration
- System Co-Design: Chip/Package/Board: Modeling and Simulation
- Characterize PCB Materials and Processing Characterization
- Apply PCB Design Tools
- Design Parallel and Memory Interfaces
- Optimize High-Speed Serial Design
- Detect and Mitigate Jitter, Crosstalk, and Noise
- Leverage High-Speed Signal Processing for Equalization and Coding
- Ensure Power Integrity in Power Distribution Networks
- Achieve Electromagnetic Compatibility and Mitigate Interference
- Apply Test and Measurement Methodology
- Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques
DesignCon Technical Program Committee chair Janine Love said:
- The DesignCon technical program offers engineers practical methods for high-speed design, blending that with information on the latest challenges, materials, and technologies. Now that I am working with the DesignCon Technical Program Committee, I am very impressed by their commitment, dedication, and passion for signal integrity and power integrity, as well as their desire to anticipate and solve the latest design problems. This year's CFA reflects their dedication and expertise, and I look forward to reading the engineering community's responses detailing how they are meeting the current design challenges.
DesignCon 2014 saw some new events, including a hands-on measurement and simulation tutorial, which I attended. See DesignCon Paper & Tutorial Explain De-Embedding for more. Track 3, Wireless and Photonic Integration, was new in 2014 and will be expanded in 2015.
Each year, DesignCon kicks off with a panel of distinguished engineers, sometimes referred to as “the jitter panel.” It's a chance for engineers to hear about how test-equipment companies respond to problems in high-speed serial links. Every time speeds increase, new problems arise that didn't affect signal and power integrity at lower data rates.
DesignCon 2014 included a panel session called “EMI and SI are Related, Get Used to it,” which I moderated. It featured engineers from both the EMI and SI fields. I plan to submit an abstract for that panel again for 2015. Last year, we had just 40 minutes. For 2015, I intend to ask for a full 75-minute session. As in 2014, DesignCon 2015 features a technical track on EMI. So, submit your abstracts soon.
EE Times articles from DesignCon 2014:
- DesignCon Paper & Tutorial Explain De-Embedding
- DesignCon 2014: Test Equipment on Display
- Best-in-Test & Top Test Engineer Winners Announced
- Agilent/Keysight Keeps Focus on Innovation
- Memory Shifts Coming, Says Keynoter
- DesignCon Revs to 28 G, Beyond