DesignCon SMEs: Tough path to 25G+ high-speed signals - Embedded.com

DesignCon SMEs: Tough path to 25G+ high-speed signals

I asked five subject-matter experts (SMEs)–some of my go-to engineers in high-speed design–what are the big issues to watch for at DesignCon this month. They told me it ain't gonna be easy, but a new generation of designs with serial electrical signals zipping along at 25 Gbits/second is being born–and there's hope for an even faster generation beyond it.

[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.].

There's a hornet's nest of signaling issues handling such designs in a reliable way, they said. The good news is many of the tricks engineers will need will be described here for the first time.

“The biggest issues right now are around how we reliably get to 25G signals for 100 and 400G Ethernet, said Scott McMorrow, president and founder of Teraspeed Consulting Group.

“There are significant numbers of people having trouble making 10G work reliably, so the leap to 25G is pretty significant,” said McMorrow, a DesignCon veteran who works on an average of 20 projects a year. “The issues are all around signal loss, crosstalk and noise—it's not well covered by the standards,” he said.

The issues crop up in places as seemingly mundane as a connector that may carry a signal just fine, but not pass it on through a pc board via to a trace as well as it should. “Some connector vendors do a good job of understanding and controlling crosstalk through the whole system, others don't,” McMorrow said.

Chip packages are another culprit when the same tight arrays of balls and bumps that handled 10G signals are expected to carry 25G links, despite the fact that crosstalk scales linearly with frequency. “You have to find 2.5 times more margin or 9-10 dB—it's possible but not without spending a lot of time understanding the problem,” he said.

At the end of the day, “engineers actually have to engineer these systems now, you can't just thrown down chips and have it all magically work,” he said.

Secrets of the glass

Another DesignCon veteran and high-speed design consultant, Lee Ritchey of Speeding Edge (Glen Ellen, Calif.), will disclose fresh techniques for handling losses caused by the woven glass in pc boards. “I found a way to solve the skew problem the glass introduces in two sides of a differential pair,” said Ritchey.

A comparison of an open and uniformly spread glass weave with a 3.5 mil wire for contrast.

“A bunch of tricks have been proposed, but I have one that doesn't cost any money, so I expect it will get some attention,” he said. “I've been using it quite awhile, and have chosen not to share it with the rest of the world, but I am doing it now because I have heard so many weird things proposed that I decided I am going to speak up,” he added.

Ritchey is humble about his secret trick, noting others may have come up with their own workarounds, maybe leveraging the way DDR3 DRAMs automatically realign signal edges. “It would be nice to say we had a brilliant flash [with our technique], but the reality is we stumbled on it” after noticing how cellphones handle non-uniformity in laser drilled pc board vias, he said.

The effects of woven glass are increasingly a focal point for high-speed engineers. “We've tinkered around a lot with the resins in pc boards, and we are tinkering more with the glass now,” he said.

Ritchey recalls first coming to DesignCon about 1994 when people were working on 10 Mbit/s Ethernet products, wondering how they would ever get to 100M. Then he worked at startup Procket that built a 350-pound system with 38 10G ports, and later at another startup that packed as many 10G ports into a 22-pound 1U pizza box.

“That's still not making people happy–right now they are trying to do 100G,” he said. “This is really what DesignCon is all about,” he added.

DesignCon resources:
DesignCon Schedule Builder (program)

Lee Ritchey's DesignCon 2013 paper “Electrical signaling is not necessarily dead after 25G,” says Adam Healey, a systems architect at LSI Corp., referring to one of three papers he co-authored for DesignCon 2013.

The paper reports on a simulation Healey helped conduct showing 40G and even faster interfaces may be viable given existing and advanced serdes and signal integrity techniques. “If you assume reasonable silicon scaling, you can get healthy looking eyes at these higher speeds,” said Healey, another veteran of the event.

That opens the door for cost- and space-reduced versions of today’s four-lane, 40G Ethernet products collapsed into a single lane. It also points the way to new interfaces such as 64G Fibre Channel even though the 32G version is still being hammered out.

The faster speeds will require more sophisticated modulation techniques such as four-level pulse amplitude modulation. The hyper-efficient PAM-4 is already being written into the draft 100GBaseKP4 standard for running 100G signals over today’s 10G backplanes, Healey said.

No one has implemented such sophisticated signaling yet, Healey said, but it’s coming. “At 10G, people didn’t need it; at 25G some people want it; and going to 40G and beyond…” you may have to give it a spin despite the trade-off of lower immunity to noise, he said.

Meanwhile, a gradual transition is clearly ahead. Engineers working on brand new designs that they want to last for awhile might consider this a good time to explore use of optical channels

“A lot of technologies being considered for on-chip and chip-to-chip optics are relatively new with unknown cost and risk factors, but they deliver a clear path for bandwidth scalability,” Healey said. “Each OEM will have to make some tough decisions on a case-by-case basis about what they use,” he added.

DesignCon 2013 papers co-authored by Adam Healey:
Beyond 25G

Equalization in high-speed serial systems

Statistical analysis of serdes Like many high-speed design experts, Donald Telian is exploring the small, hidden places where problems hide. His DesignCon 2013 paper talks about losses in vias and via models.

“Most people have been staring at channels and long runs but with back drilling, vias have been problematic for a long time,” said Telian a signal integrity consultant for SI Guys (Oakhurst, Calif.). “It may be less than a tenth of a percent of the channel length, but it’s an important area,” he said.

Looking at the big picture, this DesignCon is really all about figuring out how to make the shift from 10 to 25G products, said Telian, echoing McMorrow and others. That involves work both in the passive channel and the silicon, said Telian who designed signal integrity for the original PCI bus.

Some of the new pc board materials hold promise of cutting losses nearly ten-fold, he said. As for the chips, “gates are still essentially free, and that’s turning into some really good equalization,” he added.

Engineers are moving to techniques such as three taps of decision feedback equalization to capture signals. “We started in the transmitter, now we’ve jumped to the receiver and that takes more intelligence because you are flying blind, but that’s where the action is today,” he said.

DesignCon resources:
Donald Telian’s paper on vias
Istvan Novak, a distinguished engineer helping build big iron servers at Oracle, brings at least two specific questions to DesignCon this year.

When using a time-domain reflectometer to measure impedance on today’s high-density boards the system “appears to be artificially out of spec for a number of cases,” Novak said. “This year there are significant limitations because we are pushing longer traces with higher density boards, so there’s more resistance,” he explained.

It’s no small issue, given impedance is the main metric for validating an electrical spec. “So what I am looking for is feedback from OEMs, pcb makers, maybe even some academics on solutions for this problem,” he said.

Novak also has been dogged by problems using the miniature differential probes on vector network analyzers to test an interconnect. “There are open exposed metal pieces of the contact which will have coupling between them, and currently none of the commercial calibration processes take out those interactions so we end up doing a measurement with a kind of systematic error–how do we correct for that?” he asked.

As a veteran member of the DesignCon tech advisory board, he has already had a chance to review several papers similar to those from Ritchey, Healey and Telian.

“Over the years this event has become for us the compass showing the direction to go,” he said. “If you just go and listen to what people talk about, you get a pretty good cross section of what the industry needs to address,” he said.

[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.].

DesignCon resources:
Track on test and measurement methods

Keynote by National Instruments’ business and technology fellow

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