With DesignCon 2013 approaching, I've got 10 tech questions I'd like to get answered. (We'll present Rick's first five today; five more next week – Editor.)
A big reason I'm going to the show is to keep pace with chip interfaces stepping up from five to 25 Gbits/s, boards revving from 10 to 100 Gbits/s and systems gearing up for a shift to 400 Gbits. Accordingly, my umbrella question is: What are the latest gnarly issues in signal integrity? (See Colin Johnson's Stars of DesignCon: Signal integrity in tricked-out, high-speed interconnects for some answers.)
[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.]
I know at these data rates, PCB traces start to act like radios. How doyou tune them down? I note organizers created a half day tutorial onthis topic.
DesignCon brings out the SI experts each year for a panel thrashing out the current issues. In addition, one of my go-to SI guys, consultant Eric Bogatin, will share his thoughts. (Use Chrome for the session links -editor.) Experts from Intel will join others in a separate session on both signal integrity and the newer related field of power integrity—which leads me to my second question (click to next page).
The mega Internet data center is the proving ground for power integrity questions these days. The massive server farms must be located next to power substations to get the juice they need, so every joule counts. Just how the power gets passed around efficiently is a high art.
Google engineers return to DesignCon this year to share some of their secrets of power management on a grand scale. Their paper talks about driving server processors at higher than the recommended 12V to get new levels of power efficiency.
In its turn, Intel will give a paper on power analysis tools useful for a wide range of designs from SoCs to servers. When the event is over, I expect to have a better handle on the state of the art in power integrity.
DesignCon has always been my go-to place to understand what's up in test and measurement. One evergreen panel in particular is well known for packing into an hour the issues building up over the last year. This year it includes experts from Agilent, Lecroy and Tektronix among others.
A National Instruments keynoter may shed additional light on the topic from a 30,000-foot level. Digging deeper into the details, one session will focus on how to handle the 8-Gbits/s speeds of PCI Express 3.0, and T&M companies including Rohde and Schwarz also are hosting a set of sponsored sessions to cover the waterfront of test in the gigahertz era.
Rambus will talk about its work with 2.5-D silicon interposers, and Korea's Advanced Institute of Science and Technology will deliver two papers on 3-D chip stacks—one on its work on 2.5-D designs that lay a graphics chip and memory side-by-side on a substrate.
That was the old chestnut of DesignCons past. I can't count how many panels I saw on the topic at this event and others.
These days the question has a lower profile. The cost of ASICs has risen to double-digit millions and the cost and size of FPGAs has fallen to near-consumer prices, making this issue less visceral. So don't expect a panel to break into a food fight on this topic. But if you are debating the pros and cons, there are plenty of smart people on both sides of the question who will be glad to talk with you.
You might look for them at the Cadence paper on giga-scale ASICs or the National Instruments papers on FPGA designs. Agilent is also participating in an FPGA session discussing rapid prototyping. I would not miss the Cisco keynote, on Monday Jan. 28 at noon, by vice president of engineering Bill Swift. Driving by its networking-gear needs, Cisco is one world's leading ASIC designers.
Cadence paper on 40nm giga-scale ASIC designs