As mentioned earlier in Part1 in this tutorial, while the design byemulation method previously described allows the power supply designerto do the control design in the familiars-domain andthen convert it to a discrete/digital controller,the second approach, described here, direct digital design, allowsdesign directly in z-domainwithout conversion.
|Figure6. DC-DC Converter Digital Control Loop Block Diagram|
In this approach, the sampling process by the on-chip ADC isrepresented by an ideal sampler with time period Ts. ADC can berepresented this way as compared to the model given in , since theADC gain is taken into account in the block labeled Kd and ADCconversion time is included in the computation delay block labeled Hc.The on-chip PWM module acts as a hold device.
Representing this as a zero-order-hold (ZOH), the ADC and the PWMmodule together form a sampling and hold device. The effect of suchsample and hold action is to introduce a time delay of Ts/2 or a phaselag of (omega)Ts/2 as illustrated in Figure7, below. Here a signal is sampled at time interval of Ts andthen reconstructed through ZOH. The reconstructed signal is found tolag the original signal by (omega)Ts/2 radian or 180f/fs degree.
|Figure7. Sample and Hold process in a digital system|
The s-domain transfer function  of such a device can be expressedas,
Thus we see that the effect of the sampling and hold process in adigitally controlled power supply is that it introduces an additionalphase delay of 180f/fs degree compared to an equivalent analogcontrolled power supply. Here, f is the frequency of interest, i.e. thebandwidth, where the phase is calculated.
So, for the Bode plot shown in Figure4 in Part 1, where weignored the effect of sampling and hold, the actual phase margin is atleast reduced by 18 degree (=180x25kHz/250kHz). This means that thissystem can have a PM of at most 53 degree (=71-18). In reality thiswill be further reduced by the computation delay associated with anydigital system. This explains the reason for the under-damped responseof this system as shown in Figure 5 inPart 1 .
The computation delay block Hc, models the time delay between theADC sampling instant and the subsequent PWM duty ratio update. Thistime delay is denoted by Td and the transfer function for Hc is,
In direct digital design approach, the continuous time power stagemodel is first discretized with ZOH and the sampler. Once this isavailable, the discrete-time compensator. i.e., a digital controllerGc(z) is designed directly in the z-domain using methods similar to thecontinuous-time frequency response methods.
This has the advantage that the poles and zeros of the digitalcontrollers are located directly, resulting in a better load transientresponse, as well as better phase margin and bandwidth for the closedloop power converter. The discrete-time transfer function Gp(z) of theconverter plant, including the ZOH, the sampler, the voltage sensinggain Kd and the computation delay  model Hc is,
Vin=5.0; Vo=1.6; Io=16; Kd=0.5;L=1e-6; C=1620e-6; Rc=4e-3;RL=Vo/Io; Ts=4.0e-6; Td=0.0*Ts; num_Gps=Vin*[Rc*C 1];denom_Gps=[L*C*(1+Rc/RL) (L/RL+Rc*C) 1];Gps_dly=tf(num_Gps,denom_Gps,'inputdelay',Td); %s-domain plant withcomputation delay Td%Gpz=c2d(Gps_dly*Kd,Ts,'zoh'); %Discrete plant withZOH, Kd and Td%
The resulting discrete plant obtained from MATLAB is,
Where Kd = 1/Vomax = ½, Ts = 1/fs = 4 microsecons and thecomputation delay Td, for now, is taken as Td = 0, i.e., Hc = 1.
|Figure8. DC-DC Converter Digital Control Loop Bode Plot Gp1*Gc2 (MATLAB)|
For this plant GP1, a suitable digital controller is designed inMATLAB using the 'sisotool'. The system bandwidth is set at 27.9 kHzwith a phase margin of 61.6 deg. The Bode plot is shownin Figure 8,above . The corresponding controller GC2 is derived from MATLABas,
In discrete form, this controller is written as,
U(n) = 1.473U(n -1) – 0.4731U(n -2)+14.87E(n) – 26.91E(n -1)+12.16E(n -2)
Case 1 : Computation Delay Td =0.5Ts
For the controller just designed we assumed Td = 0, which is not thecase if we implement this controller using the sampling scheme shown inFigure 2, in Part 1. So, we recalculate Gp(z) for T= 0.5Ts to includethe effect of the sampling scheme shown in Figure 2 in Part 1 . Thus, by setting Td=0.5Ts inthe MATLAB script shown before, the modified plant model is obtainedas,
The corresponding Bode plot for this plant Gp2(z) with the controller Gc2(z) is shown in Figure 9,below. From the two plots of Gp1*Gc2 and Gp2*Gc2, it is clear that thesame controller Gc2 results in a phase margin reduction by 20.6 deg (=61.6-41.0) for the latter system. This reduction in phase margin can beaccounted for by the computation time delay of Td = 0.5Ts associatedwith Gp2. This time delay translates to a phase lag of,
where, Ts = 4uS, and f = 27kHz is the cross-over frequency atwhich the phase lag is calculated.
|Figure9. DC-DC Converter Digital Control Loop Bode Plot Gp2*Gc2 (MATLAB)|
The actual system Bode plot for the digitally controlled dc-dcconverter represented by the plant model Gp2(z) and controlled by thecontroller Gc2(z) is shown in Figure10, below .
|Figure10. DC-DC Converter Control Loop Bode Plot Gp2*Gc2 (Test result fromprototype h/w)|
Notice that the frequency domain performance parameters (bandwidth,phase margin and gain margin) agree quite well between the actual andthe designed values. The time domain dynamic performance of theconverter is shown in Figure 11, below .
|Figure11. DC-DC converter load transient reponse (Loop gain = Gp2*Gc2)|
For a step load change of 15A, the output voltage settles within28uSec (1% band). These test results on the frequency and time domaincharacteristics of the digitally controlled converter show the validityof the MATLAB based design approach as illustrated by Figure 8 and Figure 9 above .
Case 2 : Computation Delay Td =2.0Ts
The sampling scheme shown Figure 2 in Part 1 can be modified toinvestigate the effect of a more severe computation delay of Td =2.0Ts. This is easily done in software by changing the interrupt schemeand the way the actual PWM duty ratio is updated following a new ADconversion of the output voltage. Once this is done in software, thenew plant model Gp3, for Td = 2Ts, is computed using MATLAB as,
The corresponding Bode plot for this plant Gp3(z) with thecontroller Gc2(z) is shown in Figure12, below.
|Figure12. DC-DC converter digital loop control loop Bode Plot Gp3*Gc2 (MATLAB)|
From the plot of Figure 12, above ,it is clear that this system is completely unstable when controlled bythe controller Gc2. Comparing the plots of Gp1*Gc2 and Gp3*Gc2 we notethat the controller Gc2 results in a phase margin reduction by 80.6 deg[= 61.6-(-19.0)] for the latter system. This reduction in phase marginis again accounted for by the computation time delay of Td = 2.0Tsassociated with Gp3. This time delay translates to a phase lag of,
where, Ts = 4uS, and f ??27kHz is the loop cross-over frequency atwhich the phase lag is calculated. In order to find a stable controllerfor Gp3, we note that this plant has 4-poles and 2 zeros and,therefore, the 2-pole 2-zero controller Gc2 cannot stabilize thesystem. So, using MATLAB a new 3-pole 3-zero controller Gc3 is designedas,
|Figure13. DC-DC Converter Digital Control Loop Bode Plot Gp3*Gc3 (MATLAB)|
The corresponding Bode plot for this plant Gp3(z) with the newcontroller Gc3(z) is shown in Figure13, above. The actual system Bode plot for the dc-dc converterrepresented by this plant model Gp3(z) and controlled by the redesignedcontroller Gc3(z) is shown in Figure14, below . It is again clear that the frequency domaincharacteristics match very closely between the actual and the designedvalues.
|Figure14. DC-DC Converter Load Transient Response (Loop gain = Gp3*Gc3)|
Figure 15, below shows theconverter output voltage transientresponse with this controller. For a step load change of 15A, theoutput voltage settles within 50uSec (1% band). These test resultsagain show the validity of the MATLAB based design approach as depictedin Figure 12 and Figure 13 earlie r.
|Figure15. DC-DC Converter Load Transient Response (Loop gain = Gp3*Gc3)|
While both methods of digital controller design ” design by emulationand direct digital design – have their benefits to the developer, thefirst method, namely design by emulation, allows the power supplydesigners to do the control design in the familiar s-domain and thenconvert it to a discrete/digital controller.
The second approach known as direct digital design allows digitalcontroller design directly in z-domain and results in better dynamicperformance for the closed loop operation of the converter. All ofthese MATLAB based designed controllers were finally validated byexperimental results.
Toread Part 1 in this series, go toBuilding DC-DC converter systems with Direct Digital Design.
As a member of the systemsapplication team at Texas Instruments, Inc.,Shamim Choudhury's main areas of interest have been on DSP baseddigital control of switch mode power supply, UPS and motor controlsystems. Prior to his joining TI, Shamim spent two years at Alcatel,and three years at International Game Technology, as a Design Engineerworking on switch mode power supplies.
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