With digital signal processors (DSPs) getting some seriousconsideration for use in controlling power supplies, the embeddedsystems designer needs to address a number of pertinent factors in thedesign and implementation of a digital control loop. For one thing,accurate representation of the control blocks and the associatedcontrol parameters is critical for the analog designers in order toenable them to implement the DSP based digital control techniques usingthe well-known analog control design approaches.
But the result is well worth the effort. DSP based digital control allowsfor the implementation of more functional control schemes, standardcontrol hardware design for multiple platforms and flexibility of quickdesign modifications to meet specific customer needs. DSP based digitalcontrol allows for the implementation of more functional controlschemes, standard control hardware design for multiple platforms andflexibility of quick design modifications to meet specific customerneeds.
Digital controllers are also less susceptible to aging andenvironmental variations and have better noise immunity. Moreover,modern 32-bit DSP controllers, such as TMS320F280x,with their real-time code debugging capabilities, give the power supplydesigners all the benefits of digital control and allows implementationof high bandwidth, high frequency power supplies without sacrificingperformance [2-4]. The extra computing power of such processors alsoallows implementation of sophisticated nonlinear control algorithms,integrate multiple converter control into the same processor andoptimize the total system cost.
However, the power supply engineers, mostly familiar with analogcontrol design, are faced with new challenges as they start to adoptthese digital control techniques in their designs.
This article describes a step-by-step DSP based digital controldesign and implementation of a high frequency dc-dc converter,illustrating two different approaches to digital control design: designby emulation and directdigital design .
The first method, namely design by emulation, allows the powersupplydesigners to do the control design in the familiar s-domain and then convert it toa discrete/digital controller. The second approach known as directdigital design, allows digital controller design directly in z-domain.
Starting with a dc-dc buckconverter and a given set of performance specification, itdiscusses different control blocks, different control design approachesand highlights the significant differences in designing control in thedigital domain compared to the analog approach.
The two methodologies will be described in detail, first shown in MATLAB and then verified byexperimental results. In this process the effects of sampling delay andthe computation delay are also analyzed in MATLAB and then verifiedexperimentally.
The DC-DC converter setup
Figure 1 below shows asimplified block diagram of a digitallycontrolled dc-dc converter interfaced to a TMS320F280x DSP controller,with processor speed up to 100MHz and enhanced peripherals such as ahigh resolution PWM module, a12-bit A/D converter with conversion speed up to 160 nsec, a 32×32-bitmultiplier, and 32-bit timers.
|Figure1. TMS320F280x DSP based Digital Control of DC-DC Converter|
The system parameters used in this design are:
*V in =4~6V, Vout = 1.6V, Max output current Iout = 16A, R L = V out /I out = 0.1 ohm (Minimum)
*Maximum output voltage (used for ADCsignal scaling) Vomax = 2V
*PWM frequency fpwm = 250kHz; Voltageloop sampling frequency fs =250kHz
*Output filter components, L = 1.0uH,C = 1620uF, RC = 0.004 Ohm
*Desired voltage loop bandwidth fcv =20kHz
*Phase Margin = 45 deg, Settling time< 75uSec
As indicated in Figure 1 above ,a single signal measurement is needed to implement the voltage modecontrol of the dc-dc converter. The instantaneous output voltage Voutis sensed and conditioned by the voltage sense circuit and then inputto the DSP via the ADC channel. The digitized sensed output voltage Vois compared to the reference Vref.
The voltage loop controller Gc is designed to make theoutput voltage Vout track the reference Vref and at the same timeachieve the desired dynamic performance. The digitized output U of thiscontroller provides the duty ratio command for the buck regulatorswitch Q1. This command output is used to calculate the appropriatevalues for the timer compare registers in the on-chip PWM module. ThePWM module uses this value to generate the PWM output, PWM1 in thiscase, that finally drives the buck converter switch Q1.
|Figure2. DC-DC Converter Digital Control Loop Sampling Scheme|
Figure 2 above shows oneexample of a digital sampling scheme using the DSP on-chip peripherals.The sampling scheme affects the digital controller design and,therefore, needs appropriate attention. PWM output frequency is set upby configuring one of the on-chip Timers, T1 in this case. In thisexample, T1 generates a dual edge modulated (symmetric), 250 kHz PWMoutput.
These timers have associated compare registers which are used towrite the calculated duty ratio values. These values then get comparedwith the timer counter value in order to generate the PWM output. Thetime at which a newly written compare value affects the actual PWMoutput duty ratio is controlled by associated PWM control registers. Inthis example, the PWM control registers are set up such that a newvalue written in the compare register, changes the actual PWM outputduty ratio at the start of the subsequent timer (T1) period.
Also, the ADC control registers are set up such that the ADconversion is triggered at the middle of the ON pulse of the PWMoutput. As soon as the conversion is complete, the ADC module is set upto generate an interrupt. The time delay between the start of ADconversion and this interrupt is shown in Figure 2 above , as Tadc .This time includes the AD conversion time and the processor interruptlatency.
Inside the interrupt serviceroutine (ISR), the user software reads the converted valuefromthe ADC result register, implements the controller and then writes thenew PWM duty ratio value to the appropriate PWM compare register.However, this new duty ratio value takes affect at the start of thesubsequent PWM cycle. From Figure 2, it is clear that the time delayTd, between the ADC sampling instant and the PWM duty ratio update, ishalf the PWM period. In this case, the PWM period and the samplingperiod (Ts) are equal and so the computation delay is, Td = Ts/2.
Also shown in Figure 2 above, the calculation of a new duty ratio value inside the ISR is completedwell before a subsequent interrupt is generated. This means that, atthis sampling frequency, the processor bandwidth (100 MHz) allows forsufficient spare time to extend the ISR and execute multiplecontrollers or other time critical tasks. Some of this spare time canalso be used for non-time critical tasks by running them from abackground loop.
Design by Emulation
In the Design by Emulation approach, also known as Digital RedesignMethod, an analog controller isfirst designed in the continuous domain as if one were buildingcontinuous time control system, by ignoring the effects of sampling andhold associated with the AD converter and the digital PWM circuits. Theanalog controller is then converted to a discrete-time compensator bysome approximate techniques.
Figure 3 below represents asimplified block diagram of the system in Figure 1. It shows all thedifferent components of this closed loop control system in s-domain.
|Figure3. DC-DC converter congrol loop block diagram in the s-domain|
The small signal power stage model of the buck converter in s-domainis indicated as Gp(s). For the given system parameters with Vin = 5.0Vand RL = 0.1 ohm, this is derived as,
If the maximum output voltage is Vomax, then the voltage feedbackfactor is, Kd = 1/Vomax, provided that the digital output voltage Vo isrepresented in Q31 fixed-point format for this 32-bit DSP controller. The PWM modulator gain is Fm = 1. This is so because the usersoftware together with the on-chip PWM hardware can be configured suchthat as the controller output U (in Q31) varies between 0 ~ 7FFFFFFFh,the PWM output duty ratio d varies between 0 ~ 1, .
For this plant Gp(s), a suitable analog controller Gc(s) can bedesigned in MATLAB using the available control design tool called'sisotool'. The Bode plot for this design is shown in Figure 4 wherethe system bandwidth (BW) is set at 25 kHz with a phase margin (PM) of71 deg.
|Figure4: DC-DC converter control loop Bode Plot Gp(s) * GC1(s)*Kd*Fm (MATLAB)|
The corresponding controller Gc1(s) can be easily imported from theMATLAB control design toolbox. This is found as,
This analog controller Gc1(s) can be discretized by any of thecommonly used discretization methodssuch as, Bilinea r , Pole-Zero match andForward etc. [5,9]. This can be performed in MATLAB simply by writing the MATLAB scriptas:
This generates the following digital controller Gc1(z):
where, the sampling time is Ts = 1/fs = 4 microseconds. In discreteform, this controller is written as,
U(n) = 1.605U(n-1) – 0.605U(n-2)-12.34E(n) – 22.53E(n-1)_10.28E(n-2)
where, U is the control output and E is the error voltage. Thequantities with (n) denote the sampled values for the current samplingcycle, the quantities with (n-1) denote one sample old values and soon.
This controller was implemented using the TMS320F280x DSPinstruction set. During the code initialization the coefficients of theabove controller are first converted to a suitable fixed point format(Q format) in order to get the best accuracy out of this 32-bitprocessor.The fixed point format used for the controller coefficientsin this code example is Q26.
Once the controller was implemented in the DSP, its closed loopdynamic performance was tested on a prototype dc-dc converter. Thistransient load response is shown in Figure5, below .
|Figure5. DC-DC Converter Load Transient Response (loop gain = Gp*Gc1*Fm*Kd)|
For a step load change of 15A, the output voltage settles within30uSec (1% band). The converter has a satisfactory time response.However, the damping of the transient response does not reflect a phasemargin of 71 deg as shown in MATLAB Bodeplot (see Figure 4 earlier ).This difference in the designed and actual phase margin is because ofthe fact that we completely ignored the effect of sampling and hold andthe computation delay.
In the alternative digital control design method, the effect ofthese delays can be taken into account prior to the control design thatresults in a more predictable and accurate dynamic performance. This isdescribed in detail next in Part 2:Direct Digital Design of a DSP based power supply.
As a member of the systemsapplication team at Texas Instruments, Inc.,Shamim Choudhury's main areas of interest have been on DSP baseddigital control of switch mode power supply, UPS and motor controlsystems. Prior to his joining TI, Shamim spent two years at Alcatel,and three years at International Game Technology, as a Design Engineerworking on switch mode power supplies.
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