Designing Serial ATA IP into your embedded storage device design -

Designing Serial ATA IP into your embedded storage device design

Serial ATA (SATA) is a high-speed serial bus interface used to transfer data from motherboards to peripheral storage devices, such as optical disk drives, HDDs and solid state disk drives. The SATA interface is being integrated into SoCs for consumer electronic products and enterprise class storage systems, such as STBs. It is emerging as the mass storage interface of choice.

Today, it is not unusual to see terabytes of storage in the home to facilitate picture, audio and video media storage. According to IDC, the average home storage per gigabyte is predicted to outpace commercial storage by 2015.

Due to this demand, the SATA interface is increasingly becoming available as third party intellectual property (IP) to help speed development time and lower costs. The quality, completeness and interoperability of this IP become the key considerations to the SoC integrator. This article describes the SATA complete IP solution for both host and device applications.

Parallel to serial interfaces
There are a number of advantages to using high-speed serial links in place of source-synchronous parallel I/Os. Because of the advantages, the industry has moved toward high-speed serial links for applications in which performance, footprint and cost are paramount.

SATA is designed to replace the parallel ATA interface, which is sometimes referred to as IDE. The latest version of SATA operates at 3Gbit/s. However, with 8bit/10bit coding the effective clock rate becomes 300MBps. To contrast, the parallel ATA operates at 133Mbit/s.

One of the major disadvantages of the parallel interface is noise due to EMI. The parallel ATA cable contains up to 80 parallel wires and one ground shield between each signal wire to minimize EMI. Conversely, the SATA interface transmits data in serial mode, that is, one bit per time.

This is achieved by using a transceiver known as a Serdes that converts parallel data to serial data and vice-versa. Using Serdes technology, the number of pins is dramatically reduced. SATA is a full-duplex interface, which means that data conversion can take place in both directions simultaneously.

The SATA cable has seven wires—a pair for transmission, another pair for reception using differential transmission and three ground wires, all connecting to a seven pin port.

Embedded vs. discrete
When moving from parallel links to high speed serial links, ATA to SATA for example, design engineers generally are unfamiliar with the concept of embedding the clock with the data stream, and understanding performance metrics such as bit error rate and jitter. This is in contrast to users of discrete PHYs.

Consequently, vendors who offer SATA IP must understand that the PHY needs to work as a “team player.” This means that the PHY must work as just one part of a much larger, mostly digital chip that can be integrated by a design team who may be very unfamiliar with all of the high speed issues.

The requirements of the discrete PHY design, on the other hand, are very different. Usually, this composes the main part of the chip, the fabrication technology is mature with analog options for performance, and power consumption is higher.

Being the “star” of its own chip, in Table 1 below , the PHY is referred to as the “Prima Donna” PHY. Making this distinction is important— IP that originates from a discrete PHY chip is not optimized for embedding into SoC. The PHY must also interoperate with the digital portion of the SATA protocol, which is described below..

Table 1: The PHY is referred to as the “Prima Donna” PHY.

Making this distinction is important— IP that originates from a discrete PHY chip is not optimized for embedding into SoC. The PHY must also interoperate with the digital portion of the SATA protocol, which is described in the next section.

The complete SATA IP solution for both host and device applications is shown in Figure 1 below .

Figure 1: The complete SATA IP solution for both host and device applications.

It consists of three parts: the digital core controller, which supports the AHB bus interface, transport layer and link layer; the SERDES physical layer (PHY); and the verification IP (VIP), which enables configuration validation and subsystem level verification. The VIP enables both directed and constrained random methodologies, which are needed to address the SATA host and device design requirements.

Building the digital core
The industry standard interface between the software and the SATA host is the Advanced Host Controller Interface (AHCI), which allows advanced features of SATA, such as hot plug and Native Command Queuing (NCQ).

The AHCI supports multiple port implementations, which are being required in enterprise and RAID applications. Each port has its own link and transport layers. Conflicting traffic is arbitrated internally or can be brought up to the system bus level, if desired.

One of the benefits of the AHCI interface is that you can use the off-the-shelf software drivers shipped with Windows Vista and Linux. NCQ increases the hard disk drive performance by reordering the commands sent by the mother board. Connecting to the SoC bus is made possible through the AMBA interface.

The DMA is optimized for SATA transfers when integrated with the controller transport layer and bus interface, and will give the lowest latency and area compared with an external DMA solution.

Considering startup latency, as an example, it takes about eight AHB clocks counting from the internal DMA trigger event to the data being transferred on the AHB bus. For a traditional external DMA, however, it would take closer to 16 clocks or double the latency.

The DMA can offload many SATA host related tasks, such as the NCQ operation and management of the multiport configurations to increase system performance. Therefore, the whole design can run at the AHB interface frequency level to allow very large burst transfers and accommodate DMA block sizes. While the DMA does offload a significant amount of work from the software, software is still required to manage the NCQ commands.

In the digital controller, power management techniques include detecting when the SATA link is idle, which automatically initiates the transition into a power down state without software intervention.

Software will be notified via an interrupt of the state change. Also Partial and Slumber power saving modes, and the protocol to initiate them, are defined as part of the SATA specification. The decision to initiate Partial or Slumber modes can be made by the host core, rather than through software, which is a feature of AHCI.

In addition, removing the clocks during power modes can be implemented in the AHCI only feature. Along with either of the two hardware or software initiated power down modes, the PHY/link clocks can be stopped to maximize power savings.

The PHY is a mixed-signal Serdes IP designed to meet SATA connectivity for 1.5Gbit/s and 3.0Gbit/s operation, targeted to a particular fabrication process. Each SATA PHY lane takes a 10 or 20 bit input and produces a serial output at 10 or 20 times the input word rate, respectively.

The transmitted data is synchronous to the reference clock. The receiver is clock forwarded (source synchronous), and the received data and its accompanying clock are synchronous to the reference clock at the other end of the link.

The SATA PHY architecture is comprised of two sections: the transceiver with receive and the transmit circuitry, which defines one lane and the clock module. The clock module can support multiple transceivers and contains the following blocks: a multiplying PLL, which takes the input reference frequency clock and generates the internal clock for the transceiver; resistor calibration circuitry; spread spectrum generation; power on reset and the JTAG interface for test control and scan.

The transceiver needs to ensure that the transmitted signal is insensitive to process, voltage and temperature changes, and also support out of band signaling (OOB).

Production testing poses a significant challenge for highspeed serial links such as SATA. Measurements include the eye diagram (voltage and phase margin), jitter generation, jitter tolerance and other electrical parameters necessary for serial link certification.

Typically, special testing equipment, including high-speed oscilloscopes, data generators, BER tester and compliance test sets, may be necessary to verify the quality of the PHY electrical signaling.

Having visibility into the received eye is a very useful capability to indicate the link performance. Additionally, recreating the compliance eye mask during production test using a set of input and comparing the ATE vectors provides excellent test coverage in a short amount of testing time.

Consumer electronics is driving the need for mass storage devices with low power consumption and high operational performance. Applications such as personal media players, digital video recorders and notebooks need high-density storage devices such as optical disk drives, HDDs and solid state disk drives; to reliably facilitate these large amounts of data while maintaining high bandwidth, the SATA interface is used.

Designers of these applications are increasingly relying on third party IP that offers robust feature sets to help speed the development, lower overall costs and reduce risk of these storagebased SoCs. To enable a complete low-power SATA solution embedded on these SoCs, the third party IP offering must include a PHY designed and tested in the target fabrication process, a digital controller tested for interoperability in host or device applications and verification IP.

Navraj Nandr a is Director of Product Marketing for mixed signal products at Synopsys.

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