Designing SoC-based PLLs require trade-offs -

Designing SoC-based PLLs require trade-offs

PLLs (phase-locked loops) are common analogcircuits in SOCs (systems on chips). Almost allSOCs with a clock rate greater than 30 MHzuse a PLL for frequency synthesis. However, a“one-size-fits-all” PLL does not exist.

The deviceshave a range of frequency, power, area, performance,and functions. PLLs implemented in 100 nm orsmaller processes typically range in frequency from 10 MHzto 10 GHz. Their power spans from less than 1 mW to morethan 100 mW. Their size can vary from 0.04 to 2 mm2 , andtheir performance, which you typically measure as output jitter,ranges from more than 100 fsec to more than 10 psec.

The wide range of specifications is the result of the widerange of end uses. Some uses include digital-logic or processorclocking, analog-front-end ADC/DAC clocking, serial-linkcommunication, and RF synthesis. This article focuses on frequency-multiplication PLLs, but many other types exist.

Period and long-term jitter

There are many reasons for the difference in power andarea among PLLs. The most common reason is the jitterperformance, although other requirements, such as outputfrequency and loop bandwidth, also contribute. Designersshould primarily focus on period jitter and long-term jitter.Period jitter is the error that occurs when the output clockitself is acting as the trigger. In this case, you measure jitter ata hold-off time of one output period. In other words, it is theerror—that is, phase error—of one clock period. You usuallymeasure period jitter over a large number of samples of theoutput clock, and you can describe it using a peak-to-peak oran rms (root-mean-square) number.

The period jitter is of concern for static-timing analysisin digital circuits. For example, clocking a digital core at 1 GHz requires a nominal period of 1 nsec. However, no matterhow good the PLL is, only the average period is 1 nsec.For static-timing analysis, you must know the shortest periodto calculate timing margin. A high-quality PLL has periodjitter on the order of 100 fsec for a 1-GHz output. This jitterconsumes 0.01% of the output period—orders of magnitudesmaller than the uncertainty in static-timing analysis. A PLLwith minimal power consumption and area has period jitteron the order of 1 to 10 psec and consumes 0.1 to 1% of theoutput period, which is usually acceptable.

Long-term, or N-cycle, jitter is the measure of how muchthe PLL’s output-clock edge deviates from the position of anideal clock over N cycles, where N is typically thousands ofcycles. In other words, long-term jitter is a measure of the accumulated phase error. You usually measure long-term jitteras an rms value rather than a peak-to-peak value.

SOC-PLL design  requires trade-offs figure 1Long-term jitter is important in applications such as serial-link communications with embedded clocks. These applicationsinclude SONET (synchronous optical network),XAUI (10-Gbps attachment-unit interface), and data-converterclocking. For serial-link communications, manufacturerstypically specify the long-term jitter at less than 1%rms of a bit period or UI (unit interval). For example, most10-Gbps serial interfaces specify an rms long-term jitter ofless than 1 psec.

For data-converter clocking, the long-term jitter detractsfrom the SNR (signal-to-noise ratio) because SNR is1/(2×p×F×s), where F is the signal frequency, not the samplingfrequency, and s is the rms long-term jitter, which youcan assume to be of a gaussian distribution. Figure 1 providesan example of the SNR versus frequency for an ADCusing a clock with 10-psec-rms long-term jitter. High-speed,high-resolution ADCs require precise PLLs. Even 10 psec ofrms long-term jitter limits the SNR of an ADC to 10 bits atslightly more than 12 MHz, 12 bits at 3 MHz, and 14 bits atslightly less than 1 MHz.

PLL operation

SOC-PLL design  requires trade-offs figure 2The operation of the charge-pump PLL involves many trade-offs among jitter, power, and area (Figure 2 ). Manyways exist for implementing PLLs, but most integrated PLLsuse this topology. The feedback forces the output frequency,FOUT , to be equal to the input frequency, FIN , multiplied bythe feedback-divide value, according to FOUT =FIN ×M. ManyPLLs also incorporate either an input or an output divider ofvalue N to achieve a frequency FOUT =FIN ×M/N.

A detailed frequency-domain analysis concludes that thePLL has both a highpass and a lowpass function (Reference1). There is a lowpass function from input to output, meaningthat reference phase noise below the PLL’s bandwidthpasses through to the output, whereas noise higher than theloop’s bandwidth is attenuated. PLLs in noisy environmentsoften use this feature to “clean up” a reference clock by attenuatinghigh-frequency jitter.

The PLL has a highpass characteristicfor VCO (voltage-controlled-oscillator)phase noise. Thus, the PLLattenuates VCO phase noise at lowfrequencies but passes noise above theloop bandwidth to the output. Ideally,all VCO noise would be attenuatedthrough feedback, but PLLs, likeall other feedback systems, face bandwidthlimitations.

Sources of jitter

In a typical well-designed PLL, thelargest phase noise or jitter source isthe VCO. Many other noise sourcesexist, but you can usually make themsmaller than that of a VCO with amodest area or power penalty. Thecharge pump and loop filter are usuallythe next-largest noise contributors.The loop filter can be either active orpassive. In both cases, most PLLs usuallyuse a zero resistor for loop stabilization.You can also make this noiseinsignificant by lowering the resistor’s value and increasing the integrating capacitor’svalue and charge pump’s currentto keep the loop gain constant. Thisapproach has the undesired effect of increasingpower and area.

The divider blocks usually contributenegligible device noise. However, apostdivider can be a significant sourceof short-term jitter due to power-supplynoise. Supply noise can also contributeto long-term jitter through the chargepump, loop filter, and VCO, so be sureto design these blocks with sufficientsupply-noise rejection.

Jitter and bandwidth

A frequency-domain analysis showsthat jitter is suppressed below the loopbandwidth. The following time-domainexperiments show that the PLL bandwidthis the link between short- and long-term jitter. Youcan perform two time-domain experiments using a signal analyzeror a scope to measure jitter (Figure 3 and Reference2). The first experiment measures open-loop VCO jitter;the second measures the jitter of a PLL containing the VCOfrom the first experiment. Both experiments analyze the jitterby measuring the standard deviation of the zero crossings.They measure jitter versus time by using N hold-off timesfrom 1×T to N×T, where T is the nominal period.

SOC-PLL design requires trade-offs figure 3The first experiment measures the edges of an open-loopVCO. The standard deviation of the Nth zero crossingis the square root of N times the standard deviation ofone cycle (sN =s1 ×N1/2 ). The standard deviation of one cycle,s1 , is the period jitter. The value of s1 is in practice difficult to measure due to the jitterof any buffer between the VCOand the measurement instrument.The short-term jitter of the instrumentitself is also an error source.As N increases, the value of sN grows without bound, whereas therms jitter of the buffers has limits.Therefore, you can extrapolatethe value of s1 from a plot of sN versus N.

A numerical example can highlightthe difficulty in directly measurings1 . Typical buffer noise for a broadband buffer is on theorder of 30 fsec rms. The buffer noise adds in an rms way, so,for example, nine buffers with 30-fsec-rms noise in additionto the VCO with 110-fsec-rms jitter would cause no less than200-fsec-rms cycle-to-cycle jitter. Additionally, supply noisecan be as much as 100 fsec/mV on full-swing buffers, so it maybe difficult to measure period jitter of less than 200 fsec in thetime domain.

The second experiment measures the edges of a PLL withan ideal reference. The PLL contains the same VCO thatthe first experiment measured. For a few cycles, the measurementsare almost identical to those of the open-loop VCO.You can expect this result because the PLL highpass-filtersVCO noise. After many cycles, the measured standard deviationasymptotically approaches the closed-loop standarddeviation or long-term jitter, sCL . The PLL is the force thatbounds the phase error.

Figure 3 highlights a few important parameters. Theclosed-loop parameter sCL is a function of the PLL’s closed-loopbandwidth, tL , and the period jitter, s1 . The open-loopgain, which is a product of the charge-pump, loop-filter, andVCO gain divided by the feedback-divide value, determinesthe closed-loop bandwidth, a system-design parameter. Youcan calculate the closed-loop bandwidth, normalized to oneVCO period, T, as 1/(2pFL /FVCO ). You can now calculate thelong-term jitter as sCL =s1 /(4pFL /FVCO )1/2 (Reference 2).

This analysis is a simplification in at least two ways. First,the only noise source it considers is VCO phase noise. However,VCO noise limits most well-designedPLLs. Note that this analysisdoes not consider supply noise orreference noise. The second simplificationis that this analysis assumesthe PLL to be a first-order loop. MostPLLs are at least second-order loops.Many PLLs are overdamped, however,and appear almost as first-orderloops for the sake of this analysis.Additionally, the long-term jitteris a function of the square root of thebandwidth, so the error is not too severefor the sake of first-pass manualcalculations.

These experiments yield two importantresults. The first result is thatshort-term period jitter depends almostentirely on the VCO and output buffers and does not depend onthe PLL bandwidth. The second resultis that long-term jitter dependson both the VCO’s and the PLL’sbandwidth, and it improves as theVCO improves and the bandwidthincreases.

VCO phase noise

SOC-PLL design requires trade-offs figure 4A pair of equal-power, 2-GHz oscillatorsconsume several milliwatts(Figure 4 ). One oscillator is ring-based,and the other is LC-based.Three distinct regions of operation are shown in Figure 4 .The most important is the -20-dB/decade region. This regiontypically determines the period jitter of the VCO, s1 .

The plot also labels the -30-dB/decade region of theVCO. In this region, flicker device noise typically dominatesover white noise, causing the increased slope. Because flickernoise is responsible for the increased slope, the transitionfrom -30 dB/decade to -20 dB/decade is the flicker corner ofthe VCO. For ring-based VCOs, the flicker-noise corner typicallyranges from 300 kHz to 3 MHz. For LC-based VCOs,you can obtain flicker-noise corners of less than 100 kHz.You should take care to optimize the VCO for flicker noise(Reference 3).

The plots also include a flat region at high frequencies, dueto VCO output buffers. This region is important for periodjitter but typically not important for long-term jitter, as thefollowing equation shows: LdB (F)˜10×log10 [(1/PSIG )×(FOSC )2 /(Q×F)2 ]. From this equation, the phase noise drops by 3 dBfor a twofold increase in power for a given oscillator frequency.Increasing the power can be an effective way of improvingthe phase-noise performance but can become expensive.A 20-dB improvement in phase noise comes at a cost of a100-fold power increase, with all other things constant. Anotherway of improving the phase noise is to increase thequality factor of the resonant tank. Doubling the quality factorhalves the phase noise, a 6-dB improvement. The inductorstructure often limits the achievable quality factor in aCMOS process. Typical quality factors range from seven to15 and vary with many factors, includingfrequency and metal thickness.A trade-off also exists betweentuning range and quality factor inLC VCOs in which a higher qualitycomes at the expense of a smallertuning range.

There is roughly a 20-dB differencebetween the phase noise of a typicalring oscillator and that of an LC oscillatorof the same power in a deep-submicronCMOS processes. Thisdifference illustrates the phase-noiseadvantage of resonant-tank structuresfor phase noise.

As noted, the value of s1 canbe difficult to measure in the timedomain. However, it is relativelystraightforward in the frequency domain. You can calculate the VCO’s period jitter,s1 , as s1 2 =F2 ×L(F)/FOSC 3 , where F is the offsetfrequency, L(F) is the phase noise at F, and FOSC is the frequency of oscillation (Reference 4). Inthis example, the period jitter for the ring VCOwith -100 dBc/Hz at 1-MHz offset and 2-GHz oscillationfrequency is 112 fsec rms. The LC oscillatorwith -125 dBc/Hz at 1-MHz offset and2-GHz oscillation frequency results in s1 of 6.3fsec rms. These values are typically too small todirectly measure in the time domain, and bufferand scope noise obscure them.

You can calculate the long-term jitter fromthe PLL bandwidth and the corresponding valueof s1 according to sCO =s1 /(4pFL /FVCO )1/2 . Again,the calculations assume an overdamped PLL,VCO noise only, and no supply noise. Assuminga bandwidth of 100 kHz, the ring PLL with a s1 of 112 fsec would have approximately 4.5 psec rmsof long-term jitter, whereas the LC PLL with a s1 of 6.3 fsec would have a long-term jitter of 270fsec rms. If you increase the bandwidth to 1 MHz,then both long-term jitter values would decreaseby SOC-PLL design requires trade-offs square root of 10 to 1.4 and 85 fsec, respectively. You couldcontinue these calculations for higher and higherbandwidths, but many reasons exist for limitingthe bandwidth, and the jitter would not continueto decrease.

One of the primary factors limiting bandwidth is the PLL’sstability. Bandwidth is typically approximately only 1/20th ofthe reference rate for adequate phase margin. For high-performancePLLs, a low loop bandwidth mitigates reference-clockfeedthrough. Suppressing reference-clock spurs typicallyrequires a bandwidth of no more than 1/100th of the referencerate. Other reasons to limit the PLL bandwidth includedelta-sigma modulation and reference-noise, loop-filter, andcharge-pump noise suppression.

PLL area

SOC-PLL design requires trade-offs figure 5Along with performance and power, area is a major specificationfor PLLs. The performance level of a PLL largelydetermines its area. You gain a large increase in performanceby choosing an LC-based VCO rather than a ring-basedVCO. The LC-based VCOs usually measure at least 300×300microns for a design with one inductor and can be even larger.Ring oscillators, on the other hand, can measure 40×40microns or smaller. Typically, LC oscillators have a narrowertuning range than do ring oscillators. Therefore, you mustsometimes use multiple VCOs in the same PLL to achieve awide tuning range, further increasing the area.

The loop filter is another part of the PLL that significantlyincreases in area with performance. An integrated loop filtercan consume 500×500 microns or more. As the performanceof the PLL drops, you can scale down the resistors, capacitors,and charge-pump current to reduce area at the cost ofnoise. You can make a SONET/multiprotocol clocking SOC-PLL  design requires trade-offs figure 6IC in0.13-micron CMOS (Figure 5 ). The figure clearly shows thefour-core LC VCO. The PLL measures roughly 1.4 mm2 inarea. The long-term jitter is less than 500 fsec rms with a 50-kHz bandwidth. The PLL’s power dissipation is approximately 70 mW, depending on the mode of operation.

You can make a ring-based fractional-N PLLin 0.13-micron CMOS (Figure 6 ). The PLL’sarea is 0.09 mm2 , which is more than 10 timessmaller than the LC PLL example in Figure 5 .The long-term jitter is as low as 3 psec rms witha 1-MHz bandwidth, and the power consumptionis approximately 5 mW, depending on themode of operation. The area is largely digital.The digital blocks include a delta-sigma modulator,a predivider, a postdivider, feedback dividers,and control circuits. The analog area is morethan 10 times smaller than that of the LC PLLanalog area.

The two PLLs in figures 5 and 6 show why aone-size-fits-all approach does not work for SOCPLLs. The first PLL has jitter that is sufficient foralmost all SOC applications. However, the areaand power are both more than 10 times the areaand power of the second example. The long-termjitter of the second example is six times higher,however, and would be almost 20 times higher ifthe PLLs had the same bandwidth.

The driving factor for many of the trade-offsof PLL SOCs is long-term jitter. If the long-term-jitter specification is loose, you can usea small, low-power, ring-based PLL. A tighterlong-term-jitter specification entails the use of a lot of siliconarea and power to meet the requirement with an LC-basedPLL. However, for many applications between thetwo extremes, the choice is not clear, and you must performcareful analysis to optimize the PLL for power and area.

  1. Garner, Floyd M, Phaselock Techniques, Third Edition,John Wiley & Sons, 2005.
  2. McNeill, JA, “Jitter in ring oscillators,” IEEE Journal of Solid-State Circuits, Volume 32, June 1997, pg 870.
  3. Hajimiri A, and TH Lee, “A general theory of phase noise inelectrical oscillators,” IEEE Journal of Solid-State Circuits,Volume 33, February 1998, pg 179.
  4. Poore, R, “Phase Noise and Jitter,” Agilent Technologies,May 2001.

Jeff Galloway is a principal and cofounder of Silicon Creations, LLC . He received his technical education at Georgia Institute of Technology (BSEE) and Stanford University (MSEE) and previously worked as design engineer on a variety PLL, CDR, SERDES, ADC designs in CMOS, BiCMOS and bipolar technolgies.

Randy Caplan , a principal and cofounder of Silicon Creations, received a BSEE from Georgia Institute of Technology in analog/RF silicon design and has extensive design experience at MOSAID, Virtual Silicon, and Agilent Technologies.

This article has also been published on EDN Network.

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