Designing SoCbased PLLs require tradeoffs
PLLs (phaselocked loops) are common analogcircuits in SOCs (systems on chips). Almost allSOCs with a clock rate greater than 30 MHzuse a PLL for frequency synthesis. However, a“onesizefitsall” PLL does not exist.
The deviceshave a range of frequency, power, area, performance,and functions. PLLs implemented in 100 nm orsmaller processes typically range in frequency from 10 MHzto 10 GHz. Their power spans from less than 1 mW to morethan 100 mW. Their size can vary from 0.04 to 2 mm^{2} , andtheir performance, which you typically measure as output jitter,ranges from more than 100 fsec to more than 10 psec.
The wide range of specifications is the result of the widerange of end uses. Some uses include digitallogic or processorclocking, analogfrontend ADC/DAC clocking, seriallinkcommunication, and RF synthesis. This article focuses on frequencymultiplication PLLs, but many other types exist.
Period and longterm jitter
There are many reasons for the difference in power andarea among PLLs. The most common reason is the jitterperformance, although other requirements, such as outputfrequency and loop bandwidth, also contribute. Designersshould primarily focus on period jitter and longterm jitter.Period jitter is the error that occurs when the output clockitself is acting as the trigger. In this case, you measure jitter ata holdoff time of one output period. In other words, it is theerror—that is, phase error—of one clock period. You usuallymeasure period jitter over a large number of samples of theoutput clock, and you can describe it using a peaktopeak oran rms (rootmeansquare) number.
The period jitter is of concern for statictiming analysisin digital circuits. For example, clocking a digital core at 1 GHz requires a nominal period of 1 nsec. However, no matterhow good the PLL is, only the average period is 1 nsec.For statictiming analysis, you must know the shortest periodto calculate timing margin. A highquality PLL has periodjitter on the order of 100 fsec for a 1GHz output. This jitterconsumes 0.01% of the output period—orders of magnitudesmaller than the uncertainty in statictiming analysis. A PLLwith minimal power consumption and area has period jitteron the order of 1 to 10 psec and consumes 0.1 to 1% of theoutput period, which is usually acceptable.
Longterm, or Ncycle, jitter is the measure of how muchthe PLL’s outputclock edge deviates from the position of anideal clock over N cycles, where N is typically thousands ofcycles. In other words, longterm jitter is a measure of the accumulated phase error. You usually measure longterm jitteras an rms value rather than a peaktopeak value.
PLL operation
The operation of the chargepump PLL involves many tradeoffs among jitter, power, and area (Figure 2 ). Manyways exist for implementing PLLs, but most integrated PLLsuse this topology. The feedback forces the output frequency,F_{OUT} , to be equal to the input frequency, F_{IN} , multiplied bythe feedbackdivide value, according to F_{OUT} =F_{IN} ×M. ManyPLLs also incorporate either an input or an output divider ofvalue N to achieve a frequency F_{OUT} =F_{IN} ×M/N.
A detailed frequencydomain analysis concludes that thePLL has both a highpass and a lowpass function (Reference1). There is a lowpass function from input to output, meaningthat reference phase noise below the PLL’s bandwidthpasses through to the output, whereas noise higher than theloop’s bandwidth is attenuated. PLLs in noisy environmentsoften use this feature to “clean up” a reference clock by attenuatinghighfrequency jitter.
The PLL has a highpass characteristicfor VCO (voltagecontrolledoscillator)phase noise. Thus, the PLLattenuates VCO phase noise at lowfrequencies but passes noise above theloop bandwidth to the output. Ideally,all VCO noise would be attenuatedthrough feedback, but PLLs, likeall other feedback systems, face bandwidthlimitations.
Sources of jitter
In a typical welldesigned PLL, thelargest phase noise or jitter source isthe VCO. Many other noise sourcesexist, but you can usually make themsmaller than that of a VCO with amodest area or power penalty. Thecharge pump and loop filter are usuallythe nextlargest noise contributors.The loop filter can be either active orpassive. In both cases, most PLLs usuallyuse a zero resistor for loop stabilization.You can also make this noiseinsignificant by lowering the resistor’s value and increasing the integrating capacitor’svalue and charge pump’s currentto keep the loop gain constant. Thisapproach has the undesired effect of increasingpower and area.
The divider blocks usually contributenegligible device noise. However, apostdivider can be a significant sourceof shortterm jitter due to powersupplynoise. Supply noise can also contributeto longterm jitter through the chargepump, loop filter, and VCO, so be sureto design these blocks with sufficientsupplynoise rejection.
Jitter and bandwidth
The first experiment measures the edges of an openloopVCO. The standard deviation of the Nth zero crossingis the square root of N times the standard deviation ofone cycle (s_{N} =s_{1} ×N^{1/2} ). The standard deviation of one cycle,s_{1} , is the period jitter. The value of s_{1} is in practice difficult to measure due to the jitterof any buffer between the VCOand the measurement instrument.The shortterm jitter of the instrumentitself is also an error source.As N increases, the value of s_{N} grows without bound, whereas therms jitter of the buffers has limits.Therefore, you can extrapolatethe value of s_{1} from a plot of s_{N} versus N.
A numerical example can highlightthe difficulty in directly measurings_{1} . Typical buffer noise for a broadband buffer is on theorder of 30 fsec rms. The buffer noise adds in an rms way, so,for example, nine buffers with 30fsecrms noise in additionto the VCO with 110fsecrms jitter would cause no less than200fsecrms cycletocycle jitter. Additionally, supply noisecan be as much as 100 fsec/mV on fullswing buffers, so it maybe difficult to measure period jitter of less than 200 fsec in thetime domain.
The second experiment measures the edges of a PLL withan ideal reference. The PLL contains the same VCO thatthe first experiment measured. For a few cycles, the measurementsare almost identical to those of the openloop VCO.You can expect this result because the PLL highpassfiltersVCO noise. After many cycles, the measured standard deviationasymptotically approaches the closedloop standarddeviation or longterm jitter, s_{CL} . The PLL is the force thatbounds the phase error.
Figure 3 highlights a few important parameters. Theclosedloop parameter s_{CL} is a function of the PLL’s closedloopbandwidth, t_{L} , and the period jitter, s_{1} . The openloopgain, which is a product of the chargepump, loopfilter, andVCO gain divided by the feedbackdivide value, determinesthe closedloop bandwidth, a systemdesign parameter. Youcan calculate the closedloop bandwidth, normalized to oneVCO period, T, as 1/(2pF_{L} /F_{VCO} ). You can now calculate thelongterm jitter as s_{CL} =s_{1} /(4pF_{L} /F_{VCO} )^{1/2} (Reference 2).
This analysis is a simplification in at least two ways. First,the only noise source it considers is VCO phase noise. However,VCO noise limits most welldesignedPLLs. Note that this analysisdoes not consider supply noise orreference noise. The second simplificationis that this analysis assumesthe PLL to be a firstorder loop. MostPLLs are at least secondorder loops.Many PLLs are overdamped, however,and appear almost as firstorderloops for the sake of this analysis.Additionally, the longterm jitteris a function of the square root of thebandwidth, so the error is not too severefor the sake of firstpass manualcalculations.
These experiments yield two importantresults. The first result is thatshortterm period jitter depends almostentirely on the VCO and output buffers and does not depend onthe PLL bandwidth. The second resultis that longterm jitter dependson both the VCO’s and the PLL’sbandwidth, and it improves as theVCO improves and the bandwidthincreases.
VCO phase noise
The plot also labels the 30dB/decade region of theVCO. In this region, flicker device noise typically dominatesover white noise, causing the increased slope. Because flickernoise is responsible for the increased slope, the transitionfrom 30 dB/decade to 20 dB/decade is the flicker corner ofthe VCO. For ringbased VCOs, the flickernoise corner typicallyranges from 300 kHz to 3 MHz. For LCbased VCOs,you can obtain flickernoise corners of less than 100 kHz.You should take care to optimize the VCO for flicker noise(Reference 3).
The plots also include a flat region at high frequencies, dueto VCO output buffers. This region is important for periodjitter but typically not important for longterm jitter, as thefollowing equation shows: L_{dB} (F)˜10×log_{10} [(1/P_{SIG} )×(F_{OSC} )^{2} /(Q×F)^{2} ]. From this equation, the phase noise drops by 3 dBfor a twofold increase in power for a given oscillator frequency.Increasing the power can be an effective way of improvingthe phasenoise performance but can become expensive.A 20dB improvement in phase noise comes at a cost of a100fold power increase, with all other things constant. Anotherway of improving the phase noise is to increase thequality factor of the resonant tank. Doubling the quality factorhalves the phase noise, a 6dB improvement. The inductorstructure often limits the achievable quality factor in aCMOS process. Typical quality factors range from seven to15 and vary with many factors, includingfrequency and metal thickness.A tradeoff also exists betweentuning range and quality factor inLC VCOs in which a higher qualitycomes at the expense of a smallertuning range.
There is roughly a 20dB differencebetween the phase noise of a typicalring oscillator and that of an LC oscillatorof the same power in a deepsubmicronCMOS processes. Thisdifference illustrates the phasenoiseadvantage of resonanttank structuresfor phase noise.
As noted, the value of s_{1} canbe difficult to measure in the timedomain. However, it is relativelystraightforward in the frequency domain. You can calculate the VCO’s period jitter,s_{1} , as s_{1} ^{2} =F^{2} ×L(F)/F_{OSC} ^{3} , where F is the offsetfrequency, L(F) is the phase noise at F, and F_{OSC} is the frequency of oscillation (Reference 4). Inthis example, the period jitter for the ring VCOwith 100 dBc/Hz at 1MHz offset and 2GHz oscillationfrequency is 112 fsec rms. The LC oscillatorwith 125 dBc/Hz at 1MHz offset and2GHz oscillation frequency results in s_{1} of 6.3fsec rms. These values are typically too small todirectly measure in the time domain, and bufferand scope noise obscure them.
One of the primary factors limiting bandwidth is the PLL’sstability. Bandwidth is typically approximately only 1/20th ofthe reference rate for adequate phase margin. For highperformancePLLs, a low loop bandwidth mitigates referenceclockfeedthrough. Suppressing referenceclock spurs typicallyrequires a bandwidth of no more than 1/100th of the referencerate. Other reasons to limit the PLL bandwidth includedeltasigma modulation and referencenoise, loopfilter, andchargepump noise suppression.
PLL area
Along with performance and power, area is a major specificationfor PLLs. The performance level of a PLL largelydetermines its area. You gain a large increase in performanceby choosing an LCbased VCO rather than a ringbasedVCO. The LCbased VCOs usually measure at least 300×300microns for a design with one inductor and can be even larger.Ring oscillators, on the other hand, can measure 40×40microns or smaller. Typically, LC oscillators have a narrowertuning range than do ring oscillators. Therefore, you mustsometimes use multiple VCOs in the same PLL to achieve awide tuning range, further increasing the area.
You can make a ringbased fractionalN PLLin 0.13micron CMOS (Figure 6 ). The PLL’sarea is 0.09 mm^{2} , which is more than 10 timessmaller than the LC PLL example in Figure 5 .The longterm jitter is as low as 3 psec rms witha 1MHz bandwidth, and the power consumptionis approximately 5 mW, depending on themode of operation. The area is largely digital.The digital blocks include a deltasigma modulator,a predivider, a postdivider, feedback dividers,and control circuits. The analog area is morethan 10 times smaller than that of the LC PLLanalog area.
The two PLLs in figures 5 and 6 show why aonesizefitsall approach does not work for SOCPLLs. The first PLL has jitter that is sufficient foralmost all SOC applications. However, the areaand power are both more than 10 times the areaand power of the second example. The longtermjitter of the second example is six times higher,however, and would be almost 20 times higher ifthe PLLs had the same bandwidth.
The driving factor for many of the tradeoffsof PLL SOCs is longterm jitter. If the longtermjitter specification is loose, you can usea small, lowpower, ringbased PLL. A tighterlongtermjitter specification entails the use of a lot of siliconarea and power to meet the requirement with an LCbasedPLL. However, for many applications between thetwo extremes, the choice is not clear, and you must performcareful analysis to optimize the PLL for power and area.
References 

Jeff Galloway is a principal and cofounder of Silicon Creations, LLC . He received his technical education at Georgia Institute of Technology (BSEE) and Stanford University (MSEE) and previously worked as design engineer on a variety PLL, CDR, SERDES, ADC designs in CMOS, BiCMOS and bipolar technolgies.
Randy Caplan , a principal and cofounder of Silicon Creations, received a BSEE from Georgia Institute of Technology in analog/RF silicon design and has extensive design experience at MOSAID, Virtual Silicon, and Agilent Technologies.
This article has also been published on EDN Network.