Editor’s Note : In this second in a two part series, Tushar Rastogi and Subbarao Lanka of Cypress Semiconductor compare the capabilities of a standard microcontroller approach to the design of an embedded application to that of a system on chip approach, using the company’s PSoC architecture.
Using traditional approaches to system design, during any stage of the embedded system development, developers may be given new requirements that lead to a complete re-work. While developing a system using a SoC, these risks are reduced substantially as can be seen by examining more closely the gas sensing system example described in Part 1 in this series.
Making changes to an SoC design
In the case of the gas sensing system (Figure 8 ), to make the product competitive in market, the decision was made to utilize a lower cost gas sensor in the design. Now the problem arises that the output current range of this low cost sensor is lower than the previous sensor. To mitigate this problem and achieve the same performance, the system developer decides to add an op-amp in series with the existing TIA. This leads to schematic and PCB re-design when the system developer is following a traditional approach.
While using an SoC, the system developer selects the Programmable Gain Amplifier (PGA) from the component catalog and places it in the schematic of the SoC IDE.
This additional PGA compensates the reduction in the sensor output current without changing anything on the external circuit or requiring further reworking of the design.
Dealing with market driven design changes
In this scenario, a competitor launches a similar product with better precision into the market. To compete with the new product, it is decided to use a higher resolution ADC. Now the developer has to spend extra time to select a new ADC that matches the new requirements. Developers working with SoC can reconfigure the programmable components to adjust to new requirements.
For example, the ADC component in PSoC Creator provides a large range of configurability to the developer. This can be seen in the component configuration window of PSoC Creator. In our current case, the system developer can change the ADC resolution in the window to resolve the issue quickly with no impact on time to market.
Increasing the complexity level of an SoC design
Let us now see how ARM-based SoC aids in developing complicated applications such as where interrupt handling, processor efficiency, and instruction execution time play pivotal roles. Key challenges faced are:
- Interrupt Handling
- Memory footprint
- Speed of operation
- Limited hardware resources
Interrupt handling and latency. Interrupts play a key role in embedded system and application development. Interrupts provide information to the system that some event has happened and some decision is required to be taken. Interrupts are very important when the CPU is handling many tasks simultaneously.
Key challenges while handling interrupts are interrupt latency and interrupt priority. Application performance and reliability will be impacted if these key challenges are not handled properly. For example, in the gas sensing system we discussed earlier, the buzzer is driven using a software-based PWM. A timer is generally used to generate a software-based PWM. If there is latency in serving the timer ISR or its interrupt priority is low, the PWM frequency will vary, causing audile jitters in the buzzer sound.
Interrupt latency is the time difference between the arrival of an interrupt and the moment when the first instruction of the corresponding interrupt handler is fetched and executed. Interrupts must be serviced with the least possible delay. Any delay in servicing interrupts can cause embedded system failure. Interrupt latency is reduced in an ARM-based SoC through the use of the Nested Vector Interrupt Controller (NVIC). A vector table and tail chaining help achieve low interrupt latency.
The vector table contains the addresses for all exception handlers, including the reset address. It avoids software overhead and reduces interrupt latency. To reduce latency when another exception is pending, the processor does not restore all saved registers from the stack; rather, it executes the pending interrupt.
Interrupt prioritization is important in determining the order of execution when two or more interrupts occur simultaneously. Here it’s the importance, urgency, and frequency of tasks that decide priority.
Frequently occurring interrupts should be assigned a higher priority so that all interrupt requests are serviced. Otherwise, there is a possibility that multiple interrupt requests result in servicing multiple requests only once. This might occur if the second, third, or a number of interrupts occur before the first request is serviced.
ARM Cortex-M processors provide configurable interrupt priorities and efficient techniques to handle nested interrupts. The number of priority levels varies with between members of the Cortex-M family.
The ARM core must be able to service higher priority interrupts by putting lower priority interrupt execution on hold. This is required in the case of critical interrupts. ARM deploys multiple techniques to handle interrupts efficiently.
- Tail Chaining: As discussed above.
- Stack pop pre-emption: If another exception occurs during the un-stacking process of an exception, the Cortex-M abandons the operation and services the pending interrupt immediately.
- Late arrival: If an interrupt with higher priority comes while stacking of a lower priority interrupt, the Cortex-M stops the process and services the higher priority interrupt first.
Rules of thumb for interrupt handlers:
- Keep interrupt handlers as small as possible.
- Process only the essential tasks in interrupt handlers.
- Limit the overall time spent in interrupt handlers.
Memory footprint is the measure of mainmemory used or referenced by a program while it is executing. It is thesum total of program code, data variables, heap, stack, tables, etc.required for the proper working of an application.
Memoryrequirement is directly proportional to the silicon die size. Thegreater the demand for memory, the greater is the cost of the silicon.Hence, reducing memory footprint is beneficial as it results in areduction of overall system costs. ARM-based SoC helps reduce memoryfootprint by using Thumb-2 instruction technology and efficient compileroptimizations.
Thumb-2 Instruction technology: TheThumb instruction set is an extension to the 32-bit ARM architecturethat enables greater code density. The Thumb instruction set features asubset of the most commonly used 32-bit ARM instructions that have beencompressed into 16-bit wide operation codes. This results in higher codedensity and benefits developers by reducing overall memory requirementsand enable on-chip flash to be utilized to its maximum capacity.
Efficient compiler support: ARM provides efficient compilers to generate more compact and optimized code.
Other advantages of an SoC-based ARM design
Inaddition to the above outlined capabilities, the use of the ARMCortex-M in an SoC design brings with it a range of other advantagesincluding speed of operation, resource sharing, Intellectual Property(IP) protection, and lower power operation.
ARM Cortex-Mprocessors are more efficient than conventional 8/16-bit processors.Thumb-2 technology helps Cortex-M processors support 16-bit thumbinstructions. In many cases, a single thumb instruction is equivalent tomultiple 8/16-bit microcontroller instructions. This helps in achievingthe same task at lower bus speed. The low latency, 3-stage pipelinebased upon a Harvard architecture also speeds execution of instructions.
Insome SoCs, hardware resources can be shared in case of complexapplications that require more system resources than are available. Thiscan be through continuous time sharing of resources or in event ofinterrupt arrival. This can increase system utilization to more than100%.
A substantial amount ofdevelopment effort and time is spent on research in any organization. IPprotection plays a pivotal role in securing these efforts from theft.In the embedded market, competing companies may try to reverse engineerproducts by their competitors to come up with their own product. Thisaffects organization involved in innovation and research in terms ofrevenue and market share.
Two key aspects of IP protection are:
- Hiding Firmware
- Hiding Hardware
Hiding Firmware: While designing an embedded system, it is sometimes important torestrict end users from reading or writing to specific sections of theFlash memory. This prevents both corruption of data and reverseengineering of the product.
Many SoC vendors provide methods for preventing access to the Flash. These methods include:
- Making the complete Flash inaccessible for R/W
- Making parts of the Flash inaccessible for R/W
- Having different protection settings for different regions of Flash
TheARM Cortex-M processor optionally contains a Memory Protection Unit(MPU) that can be used to protect Flash access. The MPU controls accessrights to physical addresses and can support sub-regions as small as 32bytes. SoC vendors may provide additional support for protecting IPs.For example, Cypress’ PSoC 4 provides three chip-level protection modesto the embedded engineers. These modes are Open, Protected, Kill.
- Open mode: In this state, the external debugger can access system resources (Flash, SRAM, supervisory Flash, and registers) for full functional debugging of the application via the Debug Access Port (DAP).
- Protected Mode: In this state, access to system resources (Flash, SRAM, Supervisory flash, and registers) is disabled. The device can be moved to Open Mode but erases the Flash to protect illegal accesses.
- Kill Mode: In this state, the device cannot be accessed through a programmer/debugger. The device should not be put in this mode if the firmware is not complete since it will lock the SoC from further debugging/programming. It is recommended that this mode should only be enabled for production programming of an end-application that has been completely tested.
Hiding Hardware: The ARMarchitecture helps block hackers from copying the application by reverseengineering the hardware design. This helps is protecting the IPcreated by somebody/organization at hardware level.
As shown in Figure 11 ,board-level designs with discrete external components expose the systemarchitecture. It is possible to copy the design by analyzing theproduct at this level.
As shown in Figure 12 ,an SoC reduces the number of external components, taking them off thecircuit board and integrating them in the SoC. As a result, the overallhardware architecture is hidden, making it difficult to reverse engineerand copy the design.
It is still possible to reverse engineer aSoC-based design that uses fixed peripheral pins. An SoC that supportsflexible routing, where any peripheral can be routed to any pin, makesit almost impossible to understand the internal connections.
Lower power functionality
Systemsrequiring low power are needed because of growing demand for portableembedded devices like smart phones and tablets that are poweredprimarily by battery. These devices must run for a longer duration forthe same battery size or provide the same on-time using a smallerbattery. This is also important for systems that are socket powered aslower power consumption will save electricity and reduce power costs.
The primary factors determining power consumption are:
Clock speed: Inembedded designs, power consumption increases proportionally with anincrease in CPU clock speed. ARM processors are designed to provide anoptimal balance between power consumption and clock speed.
Applicationscan be designed to consume less power using an ARM-based SoC by usingmore efficient instructions (Thumb instructions). These instructionsrequire fewer clocks to execute the same task. Hence, it is possible toclock the design at a lower speed to meet functionality requirements.
Device active time: Again,power consumption increases with an increase in the active time of theprocessor. This is directly linked to execution time of the processorwhich, if less, can provide more idle time to the processor.
ARMprocessors, as discussed earlier, can quickly execute instructions anddrop into a low power mode for the time the processor is idle. In thisscenario, ARM processors provide better power figures at similar clockspeeds.
ARM Cortex-M processors with a Wake-up InterruptController (WIC) enable the processor and Interrupt unit (NVIC) to go tolow-power sleep mode. When in sleep mode, the WIC is tasked to identifyand schedule interrupts based upon priority. This functionality isimplemented using Wait-for-Interrupt (WFI), Wait-for-Event (WFE), andSend Event (SEV) instructions.
Many ARM-based SoC vendors providepower modes that can be used by systems to improve power efficiency.For example, the Cortex-M0-based PSoC 4 provides five power modes to theembedded designers, namely Active, Sleep, Deep Sleep, Hibernate, andStop, listed in order of decreasing power consumption. Stop modeconsumes current in the range of sub-nano amperes.
However, anSoC cannot remain in any single power mode. To reduce average powerconsumption, different techniques can be deployed.
Stay in lowpower mode for the majority of the time and enter active mode when atrigger occurs, then execute the exception handler and return tosleep. ARM processors are able to enter low power sleep mode when theyreturns from an exception handler to thread mode when SLEEPONEXIT isused.
Use the internal SysTick timer to wake up after regular intervals, check the necessary flags, and execute any required tasks.
Inaddition to accelerating design, lower cost, faster time to market, andbroader market applicability for the developer, an ARM-based SoCprovides several important advantages, including:
*Simple core design enables ease of integrating it into any SoC
*Area optimized processor – smaller die with reduced dynamic and leakage power
*Processors can be configured during the time of implementation as per requirements:
- Listed configuration options are available to the designer while choosing the ARM Cortex-M core for the SoC to suit the market requirements including:Configurable number of interrupts
- Support of both Endianness (little and big)
- SysTick Timer can be added based on the requirement
- Configurable debug options like Watchpoint comparators, Breakpoint comparators, and halting debug support
- Hardware Multiplier
- Ease of interfacing the processor with different on-chip peripherals
Subbarao Lanka is a Staff Applications Engineer working in Cypress Semiconductors onCapacitive Touch Sensing applications since 2007. His responsibilitiesinclude defining technical requirements for new capacitive sensingcontrollers, developing new capacitive sensing controllers, conductingsystem analysis, debugging technical issues for customers, and technicalwriting. He can be reached at .
Tushar Rastogi worked as Applications Engineer in Cypress Semiconductors. He hasworked on PSoC based applications since 2012. His responsibilitiesinclude PSoC firmware programming, application development, technicalsupport to customers with programming, and boundary scan related issuesand technical writing. He can be reached at