Designing with proven implementations of the Inter IC bus -

Designing with proven implementations of the Inter IC bus

The Inter IC (I2C) bus wasdeveloped by PhilipsSemiconductor inthe early 1980s to simplify electronic products by reducing the numberof parallel data lines. Version 1.0 of the I2C-Bus specification,released by Philips in 1992, defined a simple, 2-wire, bidirectionalbus for communications between ICs.

By 1998, the I2C bus had become the de-facto standard for low-speedIC-to-IC communications. At that time more than 50 licensed companieswere using the standard, and the I2C interface was included in morethan 1000 different ICs.

Because the I2C bus is currently the industry's most widely usedserial bus, it behooves a system designer to have a handful of provenimplementations on hand.

The method you choose – on-chip, bit-banged, or IP-coreimplementation – depends mostly on the system processor, but nothing iseasier than using an approach that is proven and already works. Thisarticle includes a working reference for each of the three methods.

The I2C bus configurations presented in this article have beenproven to ensure easy communications with slave devices on the bus.Each implementation includes examples in the form of schematics andcode.

Background and discussion
The I2C bus can operate in Standard-mode, Fast-mode, or High-Speed (Hs)mode, with maximum data rates of 100kbps (Standard mode), 400kbps (Fastmode), 1.7 Mbps Hs mode (with Cb = 400 pF), and 3.4Mbps Hsmode (with Cb = 100pF).

The original Standard-mode incorporated 7-bit addressing, whichallowed 112 slave addresses. As I2C-bus systems demanded more slavedevices, 10-bit addressing was introduced to allocate more slaveaddresses.

Fast-mode added useful features to the slave devices. The maximumdata rate was increased to 400kbps, allowing systems to transmit andreceive data four times faster. Fast-mode I2C also dropped the supportof similar buses often linked with the I2C bus, which were no longercompatible with the higher data rate.

To suppress noise spikes, fast-mode devices were given Schmitt-triggered inputs. Inaddition, the SCL and SDA lines of an I2C-bus slave device wererequired to exhibit high impedance when power was removed.

Hs-mode was created mainly to increase the data rate – up to 36times faster than that of Standard-mode. For I2C buses operating inHs-mode, the most significant change affects low-to-high transitions onthe SCL line.

Because the pull-up resistors used in Standard- and Fast-mode cannotproduce rise times fast enough to meet the Hs-mode specification, mostHs-mode systems must include active pull-ups on the SCL line. Otherchanges include an Hs-mode compatibility request, issued by the Hs-modemaster in Standard- or Fast-mode using an 8-bit master code.

If Not-Acknowledge (a bit name within the I2C frame) remains highimmediately following the master code, then all communications remainin Hs-mode until a stop occurs. The waveforms of shown in Figure 1 below illustrate the use ofthe master code for entering Hs-mode.

Figure1. These waveforms represent a transfer from Standard- or Fast-mode I2Cto Hs-mode.

Implementations for I2C on-chipperipherals
The PIC18F442microcontrollerchip includes an I2C peripheral circuit that supports Standard- andFast-mode I2C. Figure 2 below shows an applicationcircuit using that peripheral to collect samples from a 16-bitserial-output ADC. When data is received by the PIC, it is immediatelytransmitted at 115kBaud by a firmware UART.

An RS-232transceiver then allows the data to be captured by a personalcomputer's standard serial port. All assembly-source files needed toimplement Fast-mode I2C on the PIC's on-chip peripheral are containedin the downloadable I2C_on_chip_asmzip file. A tool calledMPLAB IDE Version 6.10.00 was used to develop assembly code for theFigure 2 circuit.

Figure2. The peripheral I2C circuit internal to this PIC18F442microcontroller connects to a 16-bit ADC (MAX1169).

An alternate approach usesageneral-purpose 16 bit RISC microcontroller, in thiscase the MAXQ2000,capable of operating as an I2C master in all three modes. An activepull-up is included in the microcontroller to support the 1.7MHzHs-mode. It is capable of operating as an I2C master capable ofoperating inStandard-, Fast-, or Hs-mode.

The downloadable I2C_bit_bang_asmzip file contains allassembly-source files needed to bit-bang Standard- and Fast-mode I2Csystems using the MCU's GPIO lines.

The default clock speed for the microcontroller I2C firmware is100kHz, but the MCU's 16MHz system clock allows a bit-banged I2Cinterface to run as fast as 400kHz.

The following code example shows how to capture interrupt events andhandle them in a simple interrupt-service routine. The development toolused is MAX-IDE Version 1.0 (Build Date: Nov 18 2004), which can bedownloaded for free from the Maxim website.

The downloadable I2C_bit_bang_c zipfile contains all theC-source files required to bit-bang a Standard- or Fast-mode I2C linkusing the microcontroller's GPIO lines. This example is based on amaxqi2c library consisting of the two files maxqi2c.h and maxqi2c.c.

When added to your project, these files allow 100kHz or 400kHz I2Coperation on any GPIO pin. For the C code to produce I2C at thespecified speed, however, Y1 in Figure 3 must be a 20MHz crystalinstead of a 16MHz crystal.

IAR embedded workbench IDE for the MAXQ2000 Version 1.12B (FAEEdition) was the development tool used in this case. You can registerand download a free copy of the IAR embedded workbench for the MAXQ2000(4K Kickstart Edition) at the IAR website.

The downloadable HSI2C_bit_bang_asm_czip file contains allthe assembly and C-source files required to bit-bang a 1.7MHz Hs-modeI2C link using the MCU's GPIO lines.

By mixing assembly and C code, the source code in this example takesfull advantage of the strength of each code type. Assembly optimizesspeed, and C accomplishes many things in just a few lines of code. Thetiming-critical Hs-mode I2C receive function (hsi2cRecv) is defined inthe assembly source file hsi2c.asm.

The main C-source file initializes the UART (internal to the MCU) at115.2kBaud. For the source code to produce a 1.7MHz Hs-mode I2C link,Y1 in Figure 3 must be a 20MHz crystal. The main C-source file callsthe hsi2cRecv function when needed, and a printf function transfersdata out of the on-chip UART, which is set for the 8-N-1 data format.

TheRowleyCrossWorks IDEVersion 1.0 (Build 2 Licensed copy) was the development tool used inthis example. To obtain the CrossWorks IDE, contact Rowley AssociatesLimited or visit their website.

Implementations for I2C IP Coreperipherals
An I2C IP core called DI2CM (by DigitalCore Design) is used in many CPLD and FPGA devices. TheDI2CM IPcore converts a parallel interface to an I2C interface, and implementsa true Hs-mode master capable of clock speeds as high as 3.4MHz.

One implementation makes us of the AlteraEPM3256AQC208-10 CPLD incproprating a DI2CM IP core. This circuitrequires a40MHz crystal oscillator (U3) to achieve compatibility with both 1.7MHzand 3.4MHz Hs-mode I2C.

A 3-state logic buffer with Output Enable allows the DI2CM IP coreto produce an active pull-up on the SCL line, as is required by Hs-modeI2C. Logic inverters are provided at U5, U6, and U7, to support both anactive-high and an active-low memory-mapped parallel interface.

The downloadable HSI2C_IP_core_asmzip file contains all theassembly source files needed to implement an Hs-mode I2C master. It wasobtained by interfacing the 68HC16's memory-mapped parallel interfaceto an Altera EPM3256 CPLD programmed with the DI2CM IP core. Thedevelopment tool used in this example was the Motorola 68HC MacroAssembler Version 4.1.

Ted Salazar is ApplicationsEngineering Manager at Maxim IntegratedProducts Inc., Sunnyvale, CA

Thecode for the implementations described in this article is available at'sDownloadable Code link.

1. Philips Semiconductor Staff,”The I2C-Bus Specification,” Version 2.1, January 2000. PhilipsSemiconductor document #9398 393 40011.
2. Philips Semiconductor Staff,”The I²C-bus and how to use it,” April 1995. Philips Semiconductordocument #98-8080-575-01.
3. SBS Implementers Forum,”System Management Bus (SMBus) Specification,” Version 2.0, August2000.
4. Ted Salazar, “ApplicationNote #2394,” Maxim Integrated Products, August 2003.
5. Ted Salazar, “ApplicationNote #3568,” Maxim Integrated Products, June 2005.
6. Maxim Integrated ProductsStaff, “ApplicationNote #3588,” Maxim Integrated Products, July 2005.
7. Maxim Integrated ProductsStaff, “ApplicationNote #3561,” Maxim Integrated Products, June 2005.
8. Digital Core Design Staff,”DI2CM I2C Bus Controller Master, HDL Core Specification,”

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.